Look at the in-tree "addsub" block which shows incorporation of a VHDL module
On Wed, Feb 2, 2022 at 9:04 AM Lautaro Lorenzen <[email protected]> wrote: > > Hi everyone, > > I'm starting my journey on the development of RFNoC blocks. I've always > programmed in VHDL, and although on the application notes any HDL is > supposedly usable, I can't figure out what the correct way of making the > block in VHDL is. > > With rfnocmodtool the structure that outputs is in verilog, and the same that > happens with rfnoc_create_verilog.py. I just want to write the top module aka > the functionality in VHDL, is that possible? How would that be? Are there any > examples? > > > Thanks in advance, > Regards. > Lautaro. > > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
