Emanuel,
a long time ago (I guess around 2015) we added a feature to UHD to
disable RX IQ balance tracking, as it could lead to problems in certain
scenarios. I haven't used it in a very long time so not sure about what
to expect.
You could take a look at:
set_rx_iq_balance(const bool enb, size_t chan)
and it's implementation in
lib/usrp/common/ad9361_driver/ad9361_device.cpp:2379
(set_iq_balance_auto(direction_t direction, const bool on))
and play around with it to see if it has any impact.
Hope that helps!
Cheers,
Julian
On 09.02.22 17:14, Marcus D. Leech wrote:
On 2022-02-09 01:32, [email protected] wrote:
Hi Marcus,
Thanks for thoughts on this. We also believe that is has to do with
the calibration mechanism of the AD9361, due to the very low
sub-sample delay change.
Any thoughts from the Ettus team? Is there a way to retrieve
calibration information from the RFIC in UHD? This could help to
identify if there is a correlation between calibration setting and the
group delay change.
Best regards,
Emanuel
Since UHD is an API that strives to provide an *abstraction* from the
hardware, the RFIC details are not exposed
through the usual UHD API. You will need to dive into the UHD
source code and into the low-level AD9361
driver to extract any of that information.
_______________________________________________
USRP-users mailing list -- [email protected]
To unsubscribe send an email to [email protected]
_______________________________________________
USRP-users mailing list -- [email protected]
To unsubscribe send an email to [email protected]
