Hi Ofer, I think MEM_ADDR_W should be 31 for E320. Other than that everything looks correct.
Wade On Thu, Feb 10, 2022 at 2:20 PM Ofer Saferman <[email protected]> wrote: > Hello, > > I am working on a USRP E320 unit using UHD 4.1.0.5. > I have made an FPGA image containing a radio, a 4-port replay block and a > NullSrcSink. > After investigating (with a lot of help from Rob Kossler) why my own > program doesn't work properly, per his suggestion I have tested > rfnoc_replay_samples_from_file on the 4 ports of the replay block. > Ports 0,1 work fine and the example is streaming my data. Ports 2,3 get > stuck on record and don't work properly. > Please find attached: > * 4 console logs, one for each replay port. > * My YML file with which I created the FPGA image. > * Console log of uhd_usrp_probe. > > Some further notes that might help: > * I also tried an original FPGA image of the E320 (with DUC, DDC and all > the static mapping) with the only change being that the replay block has 4 > ports (and adding 2 more endpoints). The result was the same. > * I also tried an FPGA image without the NullSrcSink. I added it sometime > in the debug process and it was just left there. It has no bearing on the > problem. > > I would appreciate any assistance to debug the issue and make all ports of > the replay block work properly. > > Regards, > Ofer Saferman > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > believed to be clean. _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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