That port contains signals that can be useful for debugging (fixing problems with the code). Currently it outputs the states of the axi_dma_master's state machines. Normally it would be disconnected, but if you were trying to understand a problem with that code then looking at the signals on that port could help.
Wade On Sun, Feb 27, 2022 at 3:53 AM sp h <[email protected]> wrote: > I am reading RFNOC replay block, end of the Verilog code I faced a debug > code ... > what's mean debug? what does it do? > > axi_dma_master #( > .AWIDTH (MEM_ADDR_W), > .DWIDTH (MEM_DATA_W) > ) axi_dma_master_i ( > // > // AXI4 Memory Mapped Interface to DRAM > // > .aclk (mem_clk), > .areset (mem_rst), > > // Write control > .m_axi_awid (m_axi_awid [ 1*i +: 1]), > .m_axi_awaddr (m_axi_awaddr [MEM_ADDR_W*i +: MEM_ADDR_W]), > .m_axi_awlen (m_axi_awlen [ 8*i +: 8]), > .m_axi_awsize (m_axi_awsize [ 3*i +: 3]), > .m_axi_awburst (m_axi_awburst [ 2*i +: 2]), > .m_axi_awvalid (m_axi_awvalid [ 1*i +: 1]), > .m_axi_awready (m_axi_awready [ 1*i +: 1]), > .m_axi_awlock (m_axi_awlock [ 1*i +: 1]), > .m_axi_awcache (m_axi_awcache [ 4*i +: 4]), > .m_axi_awprot (m_axi_awprot [ 3*i +: 3]), > .m_axi_awqos (m_axi_awqos [ 4*i +: 4]), > .m_axi_awregion (m_axi_awregion[ 4*i +: 4]), > .m_axi_awuser (m_axi_awuser [ 1*i +: 1]), > > // Write Data > .m_axi_wdata (m_axi_wdata [ MEM_DATA_W*i +: MEM_DATA_W]), > .m_axi_wstrb (m_axi_wstrb [(MEM_DATA_W/8)*i +: (MEM_DATA_W/8)]), > .m_axi_wlast (m_axi_wlast [ 1*i +: 1]), > .m_axi_wvalid (m_axi_wvalid[ 1*i +: 1]), > .m_axi_wready (m_axi_wready[ 1*i +: 1]), > .m_axi_wuser (m_axi_wuser [ 1*i +: 1]), > > // Write Response > .m_axi_bid (m_axi_bid [1*i +: 1]), > .m_axi_bresp (m_axi_bresp [2*i +: 2]), > .m_axi_buser (m_axi_buser [1*i +: 1]), > .m_axi_bvalid (m_axi_bvalid[1*i +: 1]), > .m_axi_bready (m_axi_bready[1*i +: 1]), > > // Read Control > .m_axi_arid (m_axi_arid [ 1*i +: 1]), > .m_axi_araddr (m_axi_araddr [MEM_ADDR_W*i +: MEM_ADDR_W]), > .m_axi_arlen (m_axi_arlen [ 8*i +: 8]), > .m_axi_arsize (m_axi_arsize [ 3*i +: 3]), > .m_axi_arburst (m_axi_arburst [ 2*i +: 2]), > .m_axi_arvalid (m_axi_arvalid [ 1*i +: 1]), > .m_axi_arready (m_axi_arready [ 1*i +: 1]), > .m_axi_arlock (m_axi_arlock [ 1*i +: 1]), > .m_axi_arcache (m_axi_arcache [ 4*i +: 4]), > .m_axi_arprot (m_axi_arprot [ 3*i +: 3]), > .m_axi_arqos (m_axi_arqos [ 4*i +: 4]), > .m_axi_arregion (m_axi_arregion[ 4*i +: 4]), > .m_axi_aruser (m_axi_aruser [ 1*i +: 1]), > > // Read Data > .m_axi_rid (m_axi_rid [ 1*i +: 1]), > .m_axi_rdata (m_axi_rdata [MEM_DATA_W*i +: MEM_DATA_W]), > .m_axi_rresp (m_axi_rresp [ 2*i +: 2]), > .m_axi_rlast (m_axi_rlast [ 1*i +: 1]), > .m_axi_ruser (m_axi_ruser [ 1*i +: 1]), > .m_axi_rvalid (m_axi_rvalid[ 1*i +: 1]), > .m_axi_rready (m_axi_rready[ 1*i +: 1]), > > // > // Interface for Write transactions > // > .write_addr (write_addr), > .write_count (write_count), > .write_ctrl_valid (write_ctrl_valid), > .write_ctrl_ready (write_ctrl_ready), > .write_data (write_data), > .write_data_valid (write_data_valid), > .write_data_ready (write_data_ready), > > // > // Interface for Read transactions > // > .read_addr (read_addr), > .read_count (read_count), > .read_ctrl_valid (read_ctrl_valid), > .read_ctrl_ready (read_ctrl_ready), > .read_data (read_data), > .read_data_valid (read_data_valid), > .read_data_ready (read_data_ready), > > // > // Debug > // > .debug () > ); > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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