OpenCL is not really a programming language, it is certainly not a hardware synthesis language.
OpenCL is a set of extensions/libraries to a programming language (C, C++, Python) that allow the programmer to distribute their calculations among compute units in the system, where a compute unit is some component capable of mathematical calculations. It gives the programmer a standard way to access non-traditional compute units such as GPUs and FPGAs. To be able to do this the vendor of the GPU/FPGA hardware needs to provide the OpenCL libraries to operate with their hardware - no small feat. So OpenCL would be a way to make use of the FPGA in SDRs as a compute element if it already had been programmed with some synthesis file that provides generic compute functions (that are useful to the programmer) but requires a library to get the data to the FPGA (via USB or Ethernet) for the selected mathematical operations and get the solution back. If you are doing this on sample data why would you bother (getting the data from the radio then sending it back again) when you might as well just place the logic (FPGA functions) to operate on the data stream and get/send data already processed. If you want to use the FPGA to accelerate calculations in your system then sure, you can do that but it's a lot of work. You may be able to find some open source project which already uses FPGA development boards with OpenCL and you could modify that for use with the FPGA you have access to. But the FPGA in the hardware you have alluded to is not particularly powerful and the overhead of moving the data on and off the FPGA probably would mitigate against any acceleration you would achieve. But the bottom line is that you have not changed the FPGA functionality in any way through OpenCL, you are just making use of the function that the FPGA is already programmed with in a different way and you still need to use verilog, vhd, hls, or other synthesis languages to achieve the altered functionality. jp -----Original Message----- From: Peter Featherstone <[email protected]> Sent: Tuesday, 5 April 2022 18:14 To: [email protected] Subject: [USRP-users] Question : Ettus FPGA programming using openCL or similar WARNING: This message has originated from an untrusted source. Be mindful of attachments and embedded links. Can you program the FPGA of either a E3X0 or B2X0 series using OpenCL, SYCL or similar tooling? It would be cool if you could program the onboard FPGA using C/C++ - like tools and get real-time performance at high rates. This might be wishful thinking but it looks like this is more and more possible these days without having to touch VHDL or Verilog (at least with Intel FPGAs) Thanks Pete _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected] _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
