If there's no error message, that usually means Vivado crashed. The last time I saw this happen, it was because Vivado ran out of memory, which it does not handle gracefully. I've also seen this happen because of a mistake in the code that Vivado doesn't expect (something like double driving a signal or an unusual Verilog construct). It could also be that you found another bug in Vivado. I suggest you comment out the code in your RFNoC block and gradually uncomment it until you can narrow down what section of code is causing Vivado to fail. Hopefully you can narrow down which statement is the cause. When you run the build, monitor the memory usage to make sure that's not an issue.
Wade On Mon, Apr 25, 2022 at 3:43 AM sp h <[email protected]> wrote: > I want to develop a new RFNOC block for USRP, But In spite of that test > bench file works fine, but in making bitstream I am faced with errors... > Errors: > *How can debug [00:04:42] Process terminated. Status: Failure* > > *This is my terminal Output and a build.log file that I attached, But How > I can debug and trace (from the build.log file and terminal ) to solve my > problem?? * > * Can anyone guide me? I can not find where my code has errors ... * > *thanks in advacne* > > rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -y > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/correlate_x310_rfnoc_image_core.yml > --vivado-path=/home/sp/xilinx/Vivado > [INF] Using FPGA directory /home/sp/Documents/uhd-4.1.0.5/fpga > [INF] Selected device x310 > [INF] Using io_signatures.yml from /usr/local/share/uhd/rfnoc/core. > [INF] Using x310_bsp.yml from /usr/local/share/uhd/rfnoc/core. > [INF] Adding block description from ddc.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from fft_1x64.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from window.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from keep_one_in_n.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from split_stream.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from null_src_sink.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from fosphor.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from siggen.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from radio_1x64.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from fir_filter.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from switchboard.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from correlate.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from axi_ram_fifo_4x64.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from duc.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from addsub.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from axi_ram_fifo_2x64.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from axi_ram_fifo.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from radio.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from gain.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from logpwr.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from replay.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from radio_2x64.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from moving_avg.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Adding block description from vector_iir.yml > (/usr/local/share/uhd/rfnoc/blocks). > [INF] Writing static routing table to > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_static_router.hex > [INF] Writing image core to > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_rfnoc_image_core.v > [INF] Writing image core header to > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_rfnoc_image_core.vh > [INF] Launching build with the following settings: > [INF] * Build Directory: > /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300 > [INF] * Target: X310_HG > [INF] * Image Core File: > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_rfnoc_image_core.v > [INF] * Edge Table File: > /home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_static_router.hex > Setting up a 64-bit FPGA build environment for the USRP-X3x0... > - Vivado: Found (/home/sp/xilinx/Vivado/2019.1/bin) > > Environment successfully initialized. > make -f Makefile.x300.inc bin NAME=X310_HG ARCH=kintex7 > PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 > X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 > SFP1_10GBE=1 X310=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=x310_rfnoc_image_core.v > DEFAULT_EDGE_FILE=/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x310_static_router.hex > make[1]: Entering directory > '/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300' > make[1]: Warning: File > '/home/sp/Documents/rfnoc-transceiver/rfnoc/fpga/rfnoc_block_correlate/Makefile.srcs' > has modification time 958611 s in the future > BUILDER: Checking tools... > * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) > * Python 3.8.10 > * Vivado v2019.1 (64-bit) > Using parser configuration from: > /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/dev_config.json > [00:00:00] Executing command: vivado -mode batch -source > /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/build_x300.tcl -log > build.log -journal x300.jou > CRITICAL WARNING: [filemgmt 20-1440] File > '/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v' > already exists in the project as a part of sub-design file > '/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. > Explicitly adding the file outside the scope of the sub-design can lead to > unintended behaviors and is not recommended. > [00:00:25] Current task: Initialization +++ Current Phase: Starting > [00:00:25] Current task: Initialization +++ Current Phase: Finished > [00:00:25] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2 > -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define > SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define X310=1 > -verilog_define GIT_HASH=32'hffffffff -verilog_define > RFNOC_EDGE_TBL_FILE=/home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x310_static_router.hex > -verilog_define > UHD_FPGA_DIR=/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/../.. > [00:00:25] Starting Synthesis Command > [00:04:41] Current task: Synthesis +++ Current Phase: Starting > [00:04:42] Current task: Synthesis +++ Current Phase: Finished > [00:04:42] Process terminated. Status: Failure > > ======================================================== > Warnings: 313 > Critical Warnings: 1 > Errors: 0 > > make[1]: *** [Makefile.x300.inc:127: bin] Error 1 > make[1]: Leaving directory > '/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300' > make: *** [Makefile:85: X310_HG] Error 2 > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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