On Wed, May 11, 2022 at 2:18 PM Marcus D. Leech <[email protected]> wrote:
> On 2022-05-11 14:10, [email protected] wrote: > > > > A question for anyone: when changing the frequency of a DUC (or DDC) > > would you expect the output of the block to be phase continuous > > through the change? Phase-continuous behavior would be typical for > > many DDC implementations, but with the RFNoc block I am seeing big, > > arbitrary phase jumps with the tune frequency change….. > > > > > I don't think that phase-continuity across DUC/DDC configuration was > ever a design goal, from what I recall... > Can be an easy fix since it's explicitly zeroized here when any new phase increment is valid: https://github.com/EttusResearch/uhd/blob/5333d3d12ffc21229ec4203a9ea1c7f68d82e57f/fpga/usrp3/lib/rfnoc/ddc.v#L205 Brian
_______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
