Hello, I am also currently developing with UHD v4.1.0.5 and the default verilog template code generated by *rfnoc_mod_tool *does not automatically include ce_clk.
If you would like to use ce_clk you can use the *rfnoc_create_verilog* tool to regenerate and customize the verilog code from the template with parameters you specify in your block .YML file. Example: python3 $PATH_TO_UHD_DIR/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py -c $PATH_TO_BLOCK_YML/yourblock.yml -d $DESIRED_PATH/rfnoc_block_yourblock If you are more interested in as to what the various clocks are intended to be used for, the general explanation is that certain parts of RFNoC are designed to operate at the primary bus clock of the USRP, yet one's logic may need to operate at a different clock, especially if it was designed to operate at a specific frequency... so the customizability is built into RFNoC. The following RFNoC 4 Workshop video may help provide more of a deep-dive: https://www.youtube.com/watch?v=M9ntwQie9vs There are also a few other slide materials (some from RFNoC 3 but are still useful). Recommend going into the RFNoC 4 Migration Guide as it discusses the differences if you have prior experience working with RFNoC 3 Slides: Part 1: Overview of RFNoC 4 - https://kb.ettus.com/images/5/5b/rfno... <https://www.youtube.com/redirect?event=video_description&redir_token=QUFFLUhqbkZQeUJnei1iS1hkYTcyTnUwclVOOFZKMEJtZ3xBQ3Jtc0tuNnk0dlZHdjYxUXkxZzFPd2I1dnBmM2NobFRkbG9hckd0VU0yaGc2MzREeWhzNE10c25GVUxSaE9Rc0FGb2Q4em1waUphOWZxbkZ5TGh6NHpqVjRYODRqcW5fU3ZmVzVIaWtGZ1lPUlZaaTdNTmxERQ&q=https%3A%2F%2Fkb.ettus.com%2Fimages%2F5%2F5b%2Frfnoc4_workshop_slides_2020_part_1.pdf&v=M9ntwQie9vs> Part 2: Deep dive into RFNoC 4 - https://kb.ettus.com/images/e/e9/rfno... <https://www.youtube.com/redirect?event=video_description&redir_token=QUFFLUhqbmJabXRUbGJhVHNzak4wVGhNeXVXc2h4RUpkQXxBQ3Jtc0tsNlJJNGJjY0VRSWJqLTNhenZoWUhoODZ1cGJYNEVyTFRPNjl5UURxVmRuYmVmQTktMnlrWmJzMksxS1Y5b0xxd2lTaFdoTUhyYWdQM1FHMHk4bkpRQ2ZXS3R3QTI0TXJNM0hwX3h2SU5LUnJZdHM0SQ&q=https%3A%2F%2Fkb.ettus.com%2Fimages%2Fe%2Fe9%2Frfnoc4_workshop_slides_2020_part_2.pdf&v=M9ntwQie9vs> Useful Knowledge Base Application Notes: Getting Started with RFNoC in UHD 4.0 - https://kb.ettus.com/Getting_Started_... <https://www.youtube.com/redirect?event=video_description&redir_token=QUFFLUhqa2d3MFBKZzJCUW5VRFd2cFlIalR6MGtCLTZmUXxBQ3Jtc0trY0pKOWNCamw5dmd2N2NMbFl5MHFXb2JVUEdWLVZNSWk2TkZRTy03X0FuRFo5aVdSdGtialVrLTN1T0lUSGNYTy1OaGRWOUh3T0NhdWV2dTF0LVljNkxlUFBvY0pqZ2RHLTkxUmIwZEdfcmczYjY3TQ&q=https%3A%2F%2Fkb.ettus.com%2FGetting_Started_with_RFNoC_in_UHD_4.0&v=M9ntwQie9vs> RFNoC 4 Migration Guide - https://kb.ettus.com/RFNoC_4_Migratio... <https://www.youtube.com/redirect?event=video_description&redir_token=QUFFLUhqbkhKQ09JV3gyQXplRGo2X29ibXR1bXFHUENUUXxBQ3Jtc0ttZV9ma1VZU2RDNWhpNEUxM0FDSWxiQTZwS0V2RHpMalRkWnZ6VVAtUUZXOWk1T0REWE5WMDVwcXM5QlNFRGhLSkNGY3dlRkxYZ1NzTHVDSWZJTFhlUE83dG9KbzdiWUsyMXlFUmVrMXVQUTNzOUsyOA&q=https%3A%2F%2Fkb.ettus.com%2FRFNoC_4_Migration_Guide&v=M9ntwQie9vs> Other useful videos: Exploring RFNoC 4 with the UHD Python API - https://youtu.be/fbcxm7f-Tj0 <https://www.youtube.com/watch?v=fbcxm7f-Tj0&t=0s> RFNoC 3 workshop video - https://youtu.be/VbODcrmpLaU <https://www.youtube.com/watch?v=VbODcrmpLaU&t=0s> Hope this helps, -Jeff On Sat, May 21, 2022 at 2:33 AM sp h <stackprogra...@gmail.com> wrote: > when I examine RFNOC block that is in the below path, I am faced with a > wire ce_clk and ce_rst, but in rfnoc-example there is not a ce_clk. > > uhd-4.1.0.5/fpga/usrp3/lib/rfnoc/blocks > > Can anyone guide me ce clocks? why instead using rfnoc_chdr clk, > original blocks uses ce clock? > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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