Hello, And so I wrote one :) Greatly inspired by the axil_ctrlport_master I mentioned earlier of course. (I named it ctrlport_axil_master ;) )
Do you think that it would be useful to share it somewhere ? And the same goes for the RFNoC blocks implementing LDPC encoding/decoding, would it be useful to share them somewhere ? Thanks, Florent ----- Mail original ----- De: "Wade Fife" <[email protected]> À: "Florent Allard" <[email protected]> Cc: "usrp-users" <[email protected]> Envoyé: Mercredi 15 Juin 2022 22:23:48 Objet: Re: [USRP-users] Configure Xilinx IP using AXI4-Lite Sadly, I don't think there is one in the UHD repo. I don't know of anyone who has written one. Wade On Wed, Jun 15, 2022 at 6:19 AM Florent Allard < [email protected]> wrote: > Hello, > > After having implemented into a RFNoC block the Xilinx IP LDPC Decoder and > Encoder for 5G, I’m trying to implement the Xilinx IP Polar Decoder/Encoder. > > However, the Polar IP requires to be configured with an AXI4-Lite > interface. I know that RFNoC data planes are compliant with AXI-Stream, but > is there an implementation of the AXI4-Lite protocol in the control plane > for example ? > > I found a file doing a mapping of AXI4-Lite to Ctrlport ( > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/control/axil_ctrlport_master.v), > but what I would need is the other way: receiving a ctrlport command from > RFNoC, and forwarding it as AXI4-Lite to the Xilinx IP block. Does this > exist ? > > Thank you for your help, > > Florent > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
