Hi sp, Simulation is the best way to debug issues like this. I suggest you modify the provided gain testbench to test your block. That's the best way to debug HDL code. After it's working in simulation, then you should try running it on the FPGA.
Looking at your noc_shell_gain.v, it looks like you hand-modified this file? I suggest you run rfnoc_create_verilog.py to regenerate it from the YAML file. See the getting started guide for instructions on how to use rfnoc_create_verilog. https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0 After you've generated a fresh noc_shell, do a diff between yours and the newly generated one to see what's different. Of course, this assumes you updated the YAML file correctly. Wade On Thu, Jun 16, 2022 at 4:52 AM sp h <stackprogra...@gmail.com> wrote: > I examine all of the code again and again but my problem is not solved > yet... > any RFNOC developer can not guide me? > thanks in advance > > On Tue, Jun 14, 2022 at 11:21 AM sp h <stackprogra...@gmail.com> wrote: > >> When I added ce clock domain to gain block and synthesized it, in >> Gnuradio it generates OOOO >> I attached my source code in below, can anyone guide me? I emphasize >> that I read the RFNOC FFT and replay blocks and according to them, I added >> ce clocks... >> FFT and replay block work successfully but for the gain block, it does >> not work ....Any idea? any offer? >> Thanks in advance >> > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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