Hi Stefani,
I don't think even I could find that CPLD design code. Also, I'm honestly having a very
hard time figuring out what you'd achieve by that – the CPLD really does but a tiny bit of
logic/timing glue on the UBX; what is it that you want to achieve by modifying it? Maybe
we can help you finding an alternative implementation e.g. on the FPGA or even less
work-intense in software?
Best regards,
Marcus
On 07.07.22 11:51, STEFANI, Maurizio (External) via USRP-users wrote:
HI,
I need to program the ubx-160 via FPGA using my VHDL code.
Basically the UBX-160 is managed by a PLD but I have not the data format and protocol to
be used.
Is there someone can help me with these info about the format to program the
ubx?
Thank you in advance
Maurizo stefani
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