Hi Everyone,
I’m a model-based firmware designer generating IP cores from Matlab and Simulink. I see from one of the Ettus tutorials that it is easy to include a core defined by an “xci” file, but not the “xml” descriptions from Simulink. (This was the rfnoc_block_gain exercise.) The folder in which those xml files live can be added as user repo's in Vivado, and the core is recognised, but I have issues trying to use that IP in the main design. Is this possible using the existing Ettus scripts? Many thanks, Kevin
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