Hi Adrían, Was it an error or a warning that you received? Sometimes black boxes get resolved in a later build stage.
Was the message output during the generation of the IP, or synthesis of the E320? Normally when you build the FPGA, it first builds all the IP. So I'm wondering if that step was completed successfully. Does it build without this IP? Since you're targeting a different USRP (E320 instead of X310) it'd be good to make sure that works before adding new IP. At a glance, I wonder if you should not put synth/fifo_generator_0.vhd as a part of LIB_IP_FIFO_GENERATOR_SRCS. The cmplx_mul example didn't do it that way. I think you should be able to copy the cmplx_mul example exactly, and just change the names. I don't see anything obviously wrong. Wade On Wed, Oct 5, 2022 at 4:54 AM <[email protected]> wrote: > Hi every one! > > > I´m facing some problems to synthesize a proyect that has a Xilinx IP, a > FIFO Generator. I´ve been following this example but it didnt work. > > > https://github.com/EttusResearch/uhd/tree/master/host/examples/rfnoc-example > > The synthesis return me this: > > 'fifo_generator_0' has undefined contents and is considered a black box. > The contents of this cell must be defined for opt_design to complete > successfully. > > > These are the modifications I have made: > > In rfnoc/fpga, i added the folder ip/fifo_generator_0 with the next > Makefile.inc > > include $(TOOLS_DIR)/make/viv_ip_builder.mak > > LIB_IP_FIFO_GENERATOR_SRCS = $(addprefix > $(IP_BUILD_DIR)/fifo_generator_0/, \ > > fifo_generator_0.xci \ > > synth/fifo_generator_0.vhd \ > > ) > > .INTERMEDIATE: LIB_FIFO_GENERATOR_TRGT > > $(LIB_IP_FIFO_GENERATOR_SRCS): LIB_IP_FIFO_GENERATOR_TRGT > > @: > > LIB_IP_FIFO_GENERATOR_TRGT: > $(OOT_FPGA_DIR)/ip/fifo_generator_0/fifo_generator_0.xci > > $(call > BUILD_VIVADO_IP,fifo_generator_0,$(ARCH),$(PART_ID),$(OOT_FPGA_DIR)/ip,$(IP_BUILD_DIR),0 > ) > > and in the Makefile.src of rfnoc/fpga i added: > > include $(OOT_FPGA_DIR)/ip/fifo_generator_0/Makefile.inc > > LIB_IP_XCI_SRCS += $(LIB_IP_FIFO_GENERATOR_SRCS) > > In the Makefile of my rfnoc, i added these lines: > > OOT_FPGA_DIR = $(dir $(abspath $(firstword $(MAKEFILE_LIST))))/../ > > include $(OOT_FPGA_DIR)/ip/fifo_generator_0/Makefile.inc > > Finally, I have made sure that Makefile.e320.inx had LIB_IP_XCI_SRCS. > > > How can i solve it? > > > Kind Regards > > > Adrían > > > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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