Hi, My problem is solved. By adding the option -n I force rfnoc_image_builder to use that image core that I define it.
rfnoc_image_builder -n /home/sp/rfnoc-test/rfnoc/icores/x300_rfnoc_image_core2.v On Thu, Nov 10, 2022 at 6:01 AM sp <[email protected]> wrote: > I used an RFNOC gain example file when I want to change the input of the > gain block as below....... > > > module rfnoc_block_gain #( > parameter [9:0] THIS_PORTID = 10'd0, > parameter CHDR_W = 64, > parameter [5:0] MTU = 10, > parameter NUM_PORTS = 1 > )( > // RFNoC Framework Clocks and Resets > input wire rfnoc_chdr_clk, > input wire rfnoc_ctrl_clk, > input wire ce_clk, > //Add shared reg > input wire [31:0] s_impedance, > output wire [31:0] s_threshold, > > // RFNoC Backend Interface > input wire [511:0] rfnoc_core_config, > output wire [511:0] rfnoc_core_status, > // AXIS-CHDR Input Ports (from framework) > input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata, > input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast, > input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid, > output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready, > // AXIS-CHDR Output Ports (to framework) > output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata, > output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast, > output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid, > input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready, > // AXIS-Ctrl Input Port (from framework) > input wire [31:0] s_rfnoc_ctrl_tdata, > input wire s_rfnoc_ctrl_tlast, > input wire s_rfnoc_ctrl_tvalid, > output wire s_rfnoc_ctrl_tready, > // AXIS-Ctrl Output Port (to framework) > output wire [31:0] m_rfnoc_ctrl_tdata, > output wire m_rfnoc_ctrl_tlast, > output wire m_rfnoc_ctrl_tvalid, > input wire m_rfnoc_ctrl_tready > ); > > I can not see any change in RFNOC image core ( x300_rfnoc_image_core.v).In > this file, you can see the gain definition section... > > //----------------------------------- > // gain0 > //----------------------------------- > > wire gain0_ce_clk; > wire [CHDR_W-1:0] s_gain0_in_0_tdata ; > wire s_gain0_in_0_tlast ; > wire s_gain0_in_0_tvalid; > wire s_gain0_in_0_tready; > wire [CHDR_W-1:0] m_gain0_out_0_tdata ; > wire m_gain0_out_0_tlast ; > wire m_gain0_out_0_tvalid; > wire m_gain0_out_0_tready; > > rfnoc_block_gain #( > .THIS_PORTID (9), > .CHDR_W (CHDR_W), > .NUM_PORTS (1), > .MTU (MTU) > ) b_gain0_7 ( > .rfnoc_chdr_clk (rfnoc_chdr_clk), > .rfnoc_ctrl_clk (rfnoc_ctrl_clk), > .ce_clk (gain0_ce_clk), > .rfnoc_core_config (rfnoc_core_config[512*8-1:512*7]), > .rfnoc_core_status (rfnoc_core_status[512*8-1:512*7]), > .s_rfnoc_chdr_tdata ({s_gain0_in_0_tdata }), > .s_rfnoc_chdr_tlast ({s_gain0_in_0_tlast }), > .s_rfnoc_chdr_tvalid ({s_gain0_in_0_tvalid}), > .s_rfnoc_chdr_tready ({s_gain0_in_0_tready}), > .m_rfnoc_chdr_tdata ({m_gain0_out_0_tdata }), > .m_rfnoc_chdr_tlast ({m_gain0_out_0_tlast }), > .m_rfnoc_chdr_tvalid ({m_gain0_out_0_tvalid}), > .m_rfnoc_chdr_tready ({m_gain0_out_0_tready}), > .s_rfnoc_ctrl_tdata (s_gain0_ctrl_tdata), > .s_rfnoc_ctrl_tlast (s_gain0_ctrl_tlast), > .s_rfnoc_ctrl_tvalid (s_gain0_ctrl_tvalid), > .s_rfnoc_ctrl_tready (s_gain0_ctrl_tready), > .m_rfnoc_ctrl_tdata (m_gain0_ctrl_tdata), > .m_rfnoc_ctrl_tlast (m_gain0_ctrl_tlast), > .m_rfnoc_ctrl_tvalid (m_gain0_ctrl_tvalid), > .m_rfnoc_ctrl_tready (m_gain0_ctrl_tready) > ); > > >
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