Good morning.
I am writing because I am working with the USRP E320 RAM and the AXI_RAM_FIFO
module and I am having, in my opinion, strange behaviors in memory. My goal is
to store in memory the data I receive from a point, let's call it POINT A, and
to get this data out from another point, POINT B. To do this, I have made 2
projects:
1- The first one is in a direct way. When you get to POINT A I activate the
"valid" of the block-memory transmission and at POINT B, I activate "ready" of
the block-memory transmission. In this way I have no problem. I have made tests
and I get all the data without losses.
2- The second option that I have proposed is a roundabout way. I implement 2
FIFOS before each transmission. I did this in case at some point the memory was
not available to have data and not lose continuity. However, with this
configuration I get the opposite because, contrary to option 1 where the memory
is 100% available for sending (valid always at 1) and receiving (ready always
at 1), with this configuration the memory spends many cycles without being
available for sending or receiving (valid or ready at 0).
I do not understand why the behavior of the memory with the last configuration,
since the only thing that is modified is when the valid or ready is activated.
The conversion I use in my module is CHDR to axi to receive from memory and axi
to CHDR to send to memory. The configuration parameters I use are the following:
`assign s_axis_ttimestamp = 64'b0;`
` assign s_axis_thas_time = 1'b0;`
` assign s_axis_tlength = 16'd0;`
` assign s_axis_teob = 1'b0;`
` assign s_axis_teov = 1'b0;`
Transmission valid and reception ready configuration:
\- Project 1: if Point A = ‘1’ then valid = ‘1’; if Point B = ‘1’ then
ready = ‘1’;
\- Project 2: if Point A = ‘1’ and fifo_empty1 = ‘0’ and mready = ‘1’
then valid = ‘1’
If Point B = ‘1’ and fifo_full2 =’0’ and svalid = ‘1’
then ready = ‘1’
Thank you in advance, I hope you can help me.
Best regards
Adrian CR
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