Hello Brian, Yes, it’s LMK04832 chip that generates clock on X410 and it is managed by the file that you found.
I don’t have USRP X410 but I’m trying to achieve something similar on ZCU111 running ported X410 code. I don’t know the answer regarding ZBX as I haven’t analyzed that. ZCU111 doesn’t have analog front-end so I implemented tuning on digital side, controlled in a similar way as ZBX. You won’t find schematics online for USRPs produced after \~2017. National Instruments doesn’t publish them anymore. The date coincides a bit with Ettus leaving ‘Ettus Research’, which is basically just NI brand currently. In this regard ZCU111 is more ‘free’ device than current USRPs as Xilinx published schematics and even PCB design files. Open source driver is still a very big advantage of USRPs though. X410 code is probably the most advanced and complete openly available project for RFSoC. Going back to transition to 3686.4 MHz - ZCU111 has a bit different clocking chips: LMK04208 driving three LMX2594 chips. So I won’t be able to give you ready-made solution but some instructions based on what I did: For sure you will need to add to master_to_sample_clk dict from [x4xx_rfdc_ctrl.py](https://github.com/ptrkrysik/uhd/commit/6d4d4437a6e8ebf3aba0cdddc68876f80eff79b6#diff-512da83981e88a61c70b093f36b15628ec086f429613f79abc25234548a6cfdc "mpm/python/usrp_mpm/periph_manager/x4xx_rfdc_ctrl.py") something like: 2\*153.6e6: (3.68640e9, 2, False, True),\ \ You’ll also need to modify x4xx_clk_mgr.py by adding\ 3\.6864e9: 76.8e6,\ to prc_clock_map. Then you’ll have to modify LMK04832 configuration. I would do that by: * dumping values of LMK04832 registers in default state (for clock 2949.12MHz), * importing the regs in TICSPro (https://www.ti.com/tool/TICSPRO-SW) for LMK04832, * modifying them so you get the right sample rate (3.6864GHz), PRC (pll ref clock = 76.8MHz) and sysref clock (probably PRC/24 = 3.2MHz for X410), * export registers values, * make diff with original configuration, * from that figure out what you need to change in ‘config’ function in x4xx_sample_pll.py. …or you can modify that function to just send your config if 3.6864e9 output frequency is requested. I don’t know what changes would be needed in ZBX code. At least new sample rate should be read automatically, provided you set it correctly in the ‘config’ function. So the ZBX’es expert code code will know what rfdc_rate is and from that what is current Nyquist rate. On my side I’m at the stage when streaming works for 307.2MS/s. However the signal looks ‘strange’ i.e. the band is inverted and I see something on the spectrum that looks like effect IQ imbalance. I tried to fix that by building FPGA code with increased clocks associated in any way with buses carrying samples but I’m not there yet. Best Regards,\ Piotr Krysik
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