Have plans to take a GR flowgraff and port the design to the on-board FPGA in one of the Ettus product (most likely E320). Currently, the GR flowgraff has been developed inside a Docker desktop that uses WSL under windows. The concern is that it may be non-trivial/impossible to use RFNoC to incorporate HW acceleration because communication from GNU flowgraph to FPGA and back via UHD is not supported. So far have been unable to find clear answers on Ettus site etc. Any comments? Thanks
-- Maxim Belotserkovsky [email protected] <https://gotenna.com/>
_______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
