On 20/05/2023 18:03, zhou via USRP-users wrote:
Hi,
I installed UHD 4.4 recently. I use USRP for both transmission and
receive. I find that EVM in the tail part of the captured signal is
higher, e.g., in a 20-slot capture, in the first 19 slots, EVM~= 1.2%,
but in slot#20, evm ~=2.9%.
UHD 3.10 was fine. I have found this problem in UHD 4.0 and UHD 4.1.
Now it still exists in UHD 4.4. My solution is to capture 1ms more
than what I need.
Is this a bug in FPGA?
Thanks,
Hongwei
Without telling us what you mean by a "slot", and exactly how you're
capturing, it's impossible to say. Remember, applications
of USRPs are *incredibly diverse*, so if you're using nomenclature
that is specific to your particular work, others may not
understand what it is you're doing. Please be more specific.
My guess is that you're doing a timed capture for an exact number of
samples, and that timing has become a bit more
"tight" in more recent releases, so you're capturing samples as the
receiver is shutting down, or the transmitter is
shutting down.
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