Hello, I am currently working on receiving for a 500 Mhz sampling rate with a custom block on the x410. However, I am unsure how to address the larger CHDR width, which does not seem to be handled in the example blocks provided.
To create my custom block, I started with the example provided “Keep_One_In_N.” In it, it appears it expects a CHDR_W of 64, and outputs an AXI-Stream of 32 data bits wide along with a clock(ce_clk) that is twice the frequency of the radio block clock frequency. However, if I increase the CHDR_W to 128, I get overflows, and my guess is because it is trying to send 4 samples in series instead of 4 in parallel, but the ce_clk can not keep up since it only goes at twice the rate of the radio clock. My question is what exactly is the “expected” way to edit the chdr_to_axis/axis_to_chdr modules so that my custom block works with the 128 CHDR_W. 1. Do I need to provide a “4x_clk"? I did not see one coming out of the RFDC so it seems like I would have to generate one myself. 2. Do I adjust “ITEM_W” from 32 to 64. This would mean that chdr_to_axis would take in 4 in parallel and output 2 samples in parallel, instead of output 1 sample in parallel. 3. Some other way. Thanks, Joe
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