I attempted to build an FPGA image on the UHD-4.4 branch with Vivado v2021.1_AR76780 (64-bit) using:
**make X410_X4_200 SYNTH=1 GUI=1** When the IP cores are generated, the following folder is not pulled in properly: **uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma_ex/imports** As a temporary work-around, I was able to generate the example files from the xci file in **uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma** and then copied the imports into my build directory and kicked off synthesis once again via GUI. There was also a syntax error in x410_200_rfnoc_image_core.v. The forward ticks on line 182 were causing an issue: **localparam EDGE_TBL_FILE = \`"\`RFNOC_EDGE_TBL_FILE\`";** Can someone provide some guidance? I’m not sure if I made a mistake when I pulled something in, or I’m one of the few that attempted to build the image. Going forward, I need to make clock modifications and wanted to get a look at the clock structure in vivado to find the best path forward. To summarize, I need to change the 245.76 clocks to 204.8. I would also like to use the RFDC directly if possible (static configuration is fine). That would give me what I need without the DUC/DDC RFNoC blocks. If this isn’t feasible then I’ll need some rate-changing filters and additional clocks to adjust downstream. \- Ryan
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