Hello, I am trying to build the default B210 fpga project using Xilinx ISE just to confirm I can do it before investing more time in a project. I downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set up the Xilinx environment and built the fpga project
source /opt/Xilinx/14.7/ISE_DS/settings64.sh make b210 I get an error "python: No such file or directory" during the "Generating Report" part of the build like in the attached screenshots. I don't quite understand the python line before the error, but I assume it's calling check_timing.py with b200.twr as a parameter. check_timing.py is in the expected location, not sure where build-B200//b200.twr is supposed to be, but there is the touch command right before so it should be in ~uhd/fpga/usrp3/top/b200. The USRP B210 I am using wasn't connected when building the fpga project, I assume that loading the new fpga project into the USRP can be done after building it I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I guess it's not truly default. Is there something I'm missing or doing wrong?
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