Dear USRP users and Ettus support team ,
I synthesized your Vivado project for XG Ethernet from the E320 FPGA folder. I noticed that the AXI crossbar connects the e320_core design with the e320_ps side. I understand that the e320_core design processes commands based on timestamps. However, I could not find an example project for Vitis that helps me understand how this is controlled on the SDK or Vitis side. Specifically, I observed that the e320_core part is connected to the m_axi_xbar which maps to the address range 0x4001_0000 to 0x4001_3FFF. I believe the timekeeper accesses this range with specific offsets, but please correct me if I am wrong. I am aiming to develop and deploy a design on the board using Vitis. Could you please assist me with this? Thank you.
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