Hi all! I’m an FPGA developer, dragged into the Yocto world a few years ago with the move to Zynq and ZynqMP architectures. As a research group, we mainly develop on Xilinx dev boards like the ZCU102 MPSoC, and ZCU111 RFSoC.
Having recent success adding the Xillinx Deep-Learning Processor (DPU) to the FPGA fabric, building the Vitis-AI libraries into the rootfs, and accelerating ML applications on various models, we decided to move things over to an x410 to take advantage of the RFSoC in a complete SDR product. The FPGA design was straight forward, and the Make-based FPGA build scripts, which I am typically not a fan of, was quite well thought out, worked wonderfully, and was easy to modify to customize the flow, and add changes to the block design. With a little digging, it was also fairly straightforward to incorporate the changes into the XSA/device tree for use in building the rootfs. Incorporating the Vitis-AI libraries and DPU drivers into the KAS/Kirkstone/Mender/Titanium build system is another story. Long story short, after the typical, lengthy, Yocto debug process, it ultimately fails at what seems to be a kernel incompatibility between the mainline kernel and the Vitis-AI requirements. This particular time, it manifests as syntax errors in the zocl module compilation, though I suspect it is actually a cascading series of failures that can not be solved one at a time. Researching the failure on the Xilinx forum leads to assertions that certain parts of the Vitis-AI libraries (as well as many other Xilinx applications that exercise features of the FPGA) require the Xilinx fork of the Linux Kernel, linux-xlnx. Has anyone attempted to switch kernels in a UHD system, or to integrate the linux-xlnx kernel features into the UHD kernel?
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