I'm looking to save some RFNoC resources by slimming down the CHDR interface to be 128-bits for my block and, possibly, universally.
I see the CHDR_W as well as the BLOCK_CHDR_W parameters, but I also see the bus_clk is set to 200 MHz. The current 200 MHz CHDR clock @ 128-bit wide interface is slightly too slow for my sample rates, but 266 MHz (CE clk) could potentially work. Is there anything I should be wary of if I want to change the bus_clk to be the CE CLK instead of the 200 MHz clock using a 128-bit CHDR interface? Thanks, Brian
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