Hello all, I would like to be able to add constraints to a custom block in a repeatable way. For some of my blocks that exist on different FPGA images, this is required. By constraint, I really mean a false path set in an XDC file.
What I have done is a brute force method where I set a false path in timing.xdc to a single register in my block, using an absolute path to the register. The problem with this is it's only valid for that specific image and image structure. I would like to add the constraints to a "block.xdc" file in the custom block directory, and add the file to the Makefile.srcs. However, when looking at the Makefile.x300.inc file, line 96 states: # The XDC files must be read in a specific order, motherboard (TOP_SRCS) first # and then SFP (SFP_SERDES_SRCS) and DRAM (DRAM_SRCS). DESIGN_SRCS = $(abspath $(FIFO_SRCS) \ $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \ $(UDP_SRCS) $(EXTRAM_SRCS) \ $(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \ $(IOPORT2_SRCS) \ $(PACKET_PROC_SRCS) $(DSP_SRCS) \ $(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ $(LIB_IP_XCI_SRCS) \ $(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_IMAGE_CORE_SRCS) \ $(TOP_SRCS) $(SFP_SERDES_SRCS) $(DRAM_SRCS) \ ) I take the "specific order" to mean that I must add the clock after the $(DRAM_SRCS). In my block Makefile.srcs, I am planning on making an RFNOC_OOT_TIMING_SRCS variable, and then adding it after DRAM_SRCS. Is this the correct method, or is there another method that I should follow? Thanks, David
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