The X440 has a clock board (
https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_too_clocking) which
uses the LMK04832 PLL (
https://www.ti.com/lit/ds/symlink/lmk04832.pdf?ts=1772540151834) to
actually generate the RFSoC sample clock from the 10 MHz input. This PLL
output will have a phase ambiguity WRT the 10 MHz input signal because of
PLL physics, and this is why you see a random relative phase run to run. It
looks like this chip supports a synchronization input to align output clock
edges and the X440 technically has a sync input port on the front, but I
dont know if these inputs are actually connected to each other. It could be
worth looking into what the X440 Sync In does... last I checked, it didn't
actually do anything but that was at least a year ago

On Tue, Mar 3, 2026 at 2:37 PM Eugene Grayver <[email protected]>
wrote:

> I have two X440 w/ X4_200 FPGA image.  I need to get consistent phase
> between channels on USRP1 and USRP2 across multiple runs.  I must be doing
> something wrong because I observe consistent phase between channels on any
> ONE USRP, but not across two.  The phase appears to be random between the
> two on each run.
>
> Here's my setup:
>
>    - Common 10 MHz and 1 PPS
>    -
>    
> Addr0=192.168.10.2,second_addr0=192.168.11.2,mgmt_addr0=192.168.1.10,addr1=192.168.15.2,second_addr1=192.168.16.2,mgmt_addr1=192.168.1.20,time_source=external,clock_source=external
>    - I modified the 'stock' rx_samples_to_file as follows:
>    - Usrp->set_time_next_pps(uhd::time_spec_t(0.0));
>       std::this_thread::sleep_for(std::chrono::milliseconds(1000));
>       - usrp->set_command_time(uhd::time_spec_t(COMMAND_START_S, 0));
>       // Set the rate, freq, gain, etc
>       std::this_thread::sleep_for(std::chrono::milliseconds(COMMAND_START_S
>       * 1000));
>       usrp->clear_command_time();
>       - Each streamer is created in a separate thread
>       -     stream_cmd.stream_now = false;
>           // Time was reset to zero before thread was created
>           stream_cmd.time_spec  = uhd::time_spec_t(STREAM_START_S, 0);
>           rx_stream->issue_stream_cmd(stream_cmd);
>
>
> What am I missing?  I assume commands apply to both USRPs since I create a
> multi_usrp.  Do I need to explicitly specify the motherboard for some of
> the commands?
>
>
> Eugene Grayver, Ph.D.
> Principal Engineer
> 310-336-1274
> _______________________________________________
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>
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