Hi,
I am building an N320 image that is basically a repeater with static rfnoc
links as follows:
radio0 => ddc0 => my-timestamp-adjust => axi_ram_fifo => duc1 => radio1
I have a question about how to use the parameters of the axi_ram_fifo block
in order to maximize the FIFO depth. From the N320 BIST yml, I found the
following:
# These parameters match the memory interface on the N3XX
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 31
# Create four non-overlapping 32 MB buffers by default
FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000,
31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF,
31'h01FFFFFF}"
MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 =
303.819444 MHz
This indicates that there are 4 ports (later in the yml, ports 3 and 4 are
explicitly not connected). My question is: how do I configure
FIFO_ADDR_BASE and FIFO_ADDR_MASK in order to maximize the FIFO capacity?
For the case of only needing one FIFO buffer, would this be correct?
FIFO_ADDR_BASE: "{31'h00000000, 31'h00000000, 31'h00000000,
31'h00000000}"
FIFO_ADDR_MASK: "{31'h3FFFFFFF, 31'h3FFFFFFF, 31'h3FFFFFFF,
31'h3FFFFFFF}"
For the case of only needing two FIFO buffers, would this be correct?
FIFO_ADDR_BASE: "{31'h00000000, 31'h00000000, 31'h40000000,
31'h00000000}"
FIFO_ADDR_MASK: "{31'h3FFFFFFF, 31'h3FFFFFFF, 31'h3FFFFFFF,
31'h3FFFFFFF}"
My other question is related to what is the maximum axi_ram_fifo
throughput? Can I run with one port (in & out) at full streaming rate of
250 MS/s? Does the RAM bandwidth support this rate? How about if I have 2
ports (in & out) - what is the maximum rate?
Rob
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