It looks like you based this on the 200 MHz image, but you set RF_BW to 400. So, I think the radio is exceeding the transfer rate of this image. If you want 200 MHz bandwidth, then change that parameter to 200. If you want 400 MHz bandwidth, then you'll need to increase the CHDR width to 128. The X440 CHDR bus has a 200 MHz bus, so a 64-bit width limits you to less than 400 Msps.
Wade On Thu, Jul 2, 2026 at 12:54 PM Eugene Grayver <[email protected]> wrote: > Sorry for the spam — the issue with rebuild was my mistake — I had a typo > in the .yml that was being built (the one attached to previous message was > correct). > > I can now rebuild an image w/out RX DDC and w/ RX radio going nowhere. > The fixed connection is EP->DmaFIFO->DUC->Radio. > > Usrp_probe gives the expected result as shown below. > > Unfortunately running a tx-only benchmark results in an immediate and > continuous stream of 'U'. What am I missing? Is this not the expected use > pattern for DmaFIFO? > > Thanks > > ---------- > | _____________________________________________________ > | / > | | RFNoC blocks on this device: > | | > | | * 0/DUC#0 > | | * 0/DUC#1 > | | * 0/DmaFIFO#0 > | | * 0/DmaFIFO#1 > | | * 0/Radio#0 > | | * 0/Radio#1 > | _____________________________________________________ > | / > | | Static connections on this device: > | | > | | * 0/SEP#0:0==>0/DmaFIFO#0:0 > | | * 0/DmaFIFO#0:0==>0/DUC#0:0 > | | * 0/DUC#0:0==>0/Radio#0:0 > | | * 0/SEP#1:0==>0/DmaFIFO#0:1 > | | * 0/DmaFIFO#0:1==>0/DUC#0:1 > | | * 0/DUC#0:1==>0/Radio#0:1 > | | * 0/SEP#2:0==>0/DmaFIFO#0:2 > | | * 0/DmaFIFO#0:2==>0/DUC#0:2 > | | * 0/DUC#0:2==>0/Radio#0:2 > | | * 0/SEP#3:0==>0/DmaFIFO#0:3 > | | * 0/DmaFIFO#0:3==>0/DUC#0:3 > | | * 0/DUC#0:3==>0/Radio#0:3 > | | * 0/SEP#4:0==>0/DmaFIFO#1:0 > | | * 0/DmaFIFO#1:0==>0/DUC#1:0 > | | * 0/DUC#1:0==>0/Radio#1:0 > | | * 0/SEP#5:0==>0/DmaFIFO#1:1 > | | * 0/DmaFIFO#1:1==>0/DUC#1:1 > | | * 0/DUC#1:1==>0/Radio#1:1 > | | * 0/SEP#6:0==>0/DmaFIFO#1:2 > | | * 0/DmaFIFO#1:2==>0/DUC#1:2 > | | * 0/DUC#1:2==>0/Radio#1:2 > | | * 0/SEP#7:0==>0/DmaFIFO#1:3 > | | * 0/DmaFIFO#1:3==>0/DUC#1:3 > | | * 0/DUC#1:3==>0/Radio#1:3 > ------------ > > > ------------------------------ > *From:* Eugene Grayver <[email protected]> > *Sent:* Wednesday, July 1, 2026 11:03 AM > *To:* usrp-users <[email protected]> > *Subject:* Re: X440 RFNoC build with TX FIFO > > Hi, > Turns out even rebuilding the stock .yml results in the same error. Is > there something wrong with either my build or with the version of FPGA code > checked in? > Eugene. > ------------------------------ > *From:* Eugene Grayver <[email protected]> > *Sent:* Tuesday, June 30, 2026 4:33 PM > *To:* usrp-users <[email protected]> > *Subject:* X440 RFNoC build with TX FIFO > > Hi, > > I am trying to work around the underflows on the TX. > > I added a AXI DMA FIFO and rebuilt. As far as I can tell the yaml is OK, > but when I load the new bit file, > > uhd_image_loader --args > type=x4xx,addr=192.168.10.2,clock_source=internal,time_source=internal > --fpga-path > ./uhd-4.9.0.1/fpga/usrp3/top/x400//build-usrp_x440_fpga_X4_200_fifo/X440.bit > > I get an error: > > [ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: > RfnocError: Specified destination address is unreachable: 1:0 > > Note: I had to rename the resultant bit file from x4xx.bit to X440.bit to > avoid an error related to a missing .dts file (since the DTS file is > correctly named X440.dts). > > > Here's the .yml file. Note that I removed the RX DDC to reduce the FPGA > congestion. > > ----------------------- > # General parameters > # ----------------------------------------- > schema: rfnoc_imagebuilder_args # Identifier for the schema used > to validate this file > copyright: >- # Copyright information used in > file headers > Copyright 2023 Ettus Research, a National Instruments Brand > license: >- # License information used in > file headers > SPDX-License-Identifier: LGPL-3.0-or-later > version: '1.0' # File version > chdr_width: 64 # Bit width of the CHDR bus for > this image > device: 'x440' # USRP type > image_core_name: 'usrp_x440_fpga_X4_200_fifo' # Name to use for the > generated output files > default_target: 'X440' # Default make target > inherit: > - 'yaml_include/x440_radio_base.yml' > - 'yaml_include/x4xx_x4_base.yml' > > parameters: > RF_BW: 400 > ENABLE_DRAM: True > NUM_DRAM_BANKS: 2 > NUM_DRAM_CHANS: 8 > DRAM_WIDTH: 128 > > # A list of all stream endpoints in design > # ---------------------------------------- > stream_endpoints: > ep0: # Stream endpoint name > ctrl: True # Endpoint passes control traffic > data: True # Endpoint passes data traffic > buff_size_bytes: 262144 # Ingress buffer size for data > ep1: > ctrl: False > data: True > buff_size_bytes: 262144 > ep2: > ctrl: False > data: True > buff_size_bytes: 262144 > ep3: > ctrl: False > data: True > buff_size_bytes: 262144 > ep4: > ctrl: False > data: True > buff_size_bytes: 262144 > ep5: > ctrl: False > data: True > buff_size_bytes: 262144 > ep6: > ctrl: False > data: True > buff_size_bytes: 262144 > ep7: > ctrl: False > data: True > buff_size_bytes: 262144 > > # A table of which crossbar routes to include > # ------------------------------------------- > # Rows correspond to input ports and columns correspond to output ports. > # Entering a 1 includes and a 0 removes that route from the crossbar. > crossbar_routes: > # eth0 eth2 dma ep1 ep3 ep5 ep7 > # eth1 eth3 ep0 ep2 ep4 ep6 > - [ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0) > - [ 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1) > - [ 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2) > - [ 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3) > - [ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2) > - [ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3) > > # A list of all NoC blocks in design > # ---------------------------------- > noc_blocks: > radio0: > block_desc: 'radio.yml' > parameters: > NUM_PORTS: 4 > radio1: > block_desc: 'radio.yml' > parameters: > NUM_PORTS: 4 > duc0: > block_desc: 'duc.yml' > parameters: > NUM_PORTS: 4 > duc1: > block_desc: 'duc.yml' > parameters: > NUM_PORTS: 4 > fifo0: > block_desc: 'axi_ram_fifo.yml' > parameters: > NUM_PORTS: 4 > MEM_ADDR_W: 32 > MEM_DATA_W: 128 > MEM_CLK_RATE: "300e6" > # Create 4 non-overlapping 2 MB buffers > FIFO_ADDR_BASE: "{32'h00600000, 32'h00400000, 32'h00200000, > 32'h00000000}" > FIFO_ADDR_MASK: "{32'h001FFFFF, 32'h001FFFFF, 32'h001FFFFF, > 32'h001FFFFF}" > > fifo1: > block_desc: 'axi_ram_fifo.yml' > parameters: > NUM_PORTS: 4 > MEM_ADDR_W: 32 > MEM_DATA_W: 128 > MEM_CLK_RATE: "300e6" > # Create 4 non-overlapping 2 MB buffers > FIFO_ADDR_BASE: "{32'h00600000, 32'h00400000, 32'h00200000, > 32'h00000000}" > FIFO_ADDR_MASK: "{32'h001FFFFF, 32'h001FFFFF, 32'h001FFFFF, > 32'h001FFFFF}" > > # A list of all static connections in design > # ------------------------------------------ > # Format: A list of connection maps (list of key-value pairs) with the > following keys > # - srcblk = Source block to connect > # - srcport = Port on the source block to connect > # - dstblk = Destination block to connect > # - dstport = Port on the destination block to connect > connections: > # RF A:0 TX > - { srcblk: ep0, srcport: out0, dstblk: fifo0, dstport: in_0 } > - { srcblk: fifo0, srcport: out_0, dstblk: duc0, dstport: in_0 } > - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } > # RF A:1 TX > - { srcblk: ep1, srcport: out0, dstblk: fifo0, dstport: in_1 } > - { srcblk: fifo0, srcport: out_1, dstblk: duc0, dstport: in_1 } > - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } > # RF A:2 TX > - { srcblk: ep2, srcport: out0, dstblk: fifo0, dstport: in_2 } > - { srcblk: fifo0, srcport: out_2, dstblk: duc0, dstport: in_2 } > - { srcblk: duc0, srcport: out_2, dstblk: radio0, dstport: in_2 } > # RF A:3 TX > - { srcblk: ep3, srcport: out0, dstblk: fifo0, dstport: in_3 } > - { srcblk: fifo0, srcport: out_3, dstblk: duc0, dstport: in_3 } > - { srcblk: duc0, srcport: out_3, dstblk: radio0, dstport: in_3 } > # > # RF B:0 TX > - { srcblk: ep4, srcport: out0, dstblk: fifo1, dstport: in_0 } > - { srcblk: fifo1, srcport: out_0, dstblk: duc1, dstport: in_0 } > - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } > # RF B:1 TX > - { srcblk: ep5, srcport: out0, dstblk: fifo1, dstport: in_1 } > - { srcblk: fifo1, srcport: out_1, dstblk: duc1, dstport: in_1 } > - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 } > # RF B:2 TX > - { srcblk: ep6, srcport: out0, dstblk: fifo1, dstport: in_2 } > - { srcblk: fifo1, srcport: out_2, dstblk: duc1, dstport: in_2 } > - { srcblk: duc1, srcport: out_2, dstblk: radio1, dstport: in_2 } > # RF B:3 TX > - { srcblk: ep7, srcport: out0, dstblk: fifo1, dstport: in_3 } > - { srcblk: fifo1, srcport: out_3, dstblk: duc1, dstport: in_3 } > - { srcblk: duc1, srcport: out_3, dstblk: radio1, dstport: in_3 } > # > # - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: > gpio0 } > # - { srcblk: _device_, srcport: _none_, dstblk: _device_, dstport: > gpio1 } > # BSP connections are inherited from YAML include files > - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram0 } > - { srcblk: fifo1, srcport: axi_ram, dstblk: _device_, dstport: dram1 } > > - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } > - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } > - { srcblk: radio0, srcport: out_2, dstblk: ep2, dstport: in0 } > - { srcblk: radio0, srcport: out_3, dstblk: ep3, dstport: in0 } > - { srcblk: radio1, srcport: out_0, dstblk: ep4, dstport: in0 } > - { srcblk: radio1, srcport: out_1, dstblk: ep5, dstport: in0 } > - { srcblk: radio1, srcport: out_2, dstblk: ep6, dstport: in0 } > - { srcblk: radio1, srcport: out_3, dstblk: ep7, dstport: in0 } > > > > # A list of all clock domain connections in design > # ------------------------------------------------ > # Format: A list of connection maps (list of key-value pairs) with the > following keys > # - srcblk = Source block to connect (Always "_device"_) > # - srcport = Clock domain on the source block to connect > # - dstblk = Destination block to connect > # - dstport = Clock domain on the destination block to connect > clk_domains: > - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce > } > - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce > } > # Other clock domains are inherited from YAML include files > - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } > - { srcblk: _device_, srcport: dram, dstblk: fifo1, dstport: mem } > > > -------------------------------- > > > Eugene Grayver, Ph.D. > Principal Engineer > 310-336-1274 > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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