http://codereview.chromium.org/125185/diff/1/4
File src/x64/assembler-x64.cc (right):

http://codereview.chromium.org/125185/diff/1/4#newcode1232
Line 1232: emit(0x40 | (dst.code() & 0x8) >> 1| (src.code() & 0x8) >>
3);
It is a REX prefix, but the current methods expect Register, not
MMXRegister, so they didn't apply.
If we become serious about adding MMX instructions, we'll need
emit-rex's for MMX registers too. For now, I have removed it all.

http://codereview.chromium.org/125185/diff/1/5
File src/x64/assembler-x64.h (right):

http://codereview.chromium.org/125185/diff/1/5#newcode478
Line 478: void movzxq_b(Register dst, const Operand& src);
This was just a bad adoptation of the ia32 notation.
I'll change it to movzxbq (readability is ... not so impressive, though
:)
Eventually, I guess we'll have an mxyzptlk instruction for something.

http://codereview.chromium.org/125185/diff/1/5#newcode814
Line 814:
For now we just use plain old f-operations. I'll remove these again,
since I didn't use them anyway.

http://codereview.chromium.org/125185/diff/1/6
File src/x64/codegen-x64.cc (right):

http://codereview.chromium.org/125185/diff/1/6#newcode554
Line 554: __ addq(rax, rbx);  // add optimistically
On 2009/06/17 08:27:48, William Hesse wrote:
> I think we want addl here.  If our smis are zero-extended 32-bit smis,
then we
> want the overflow flag to indicate an overflow into bit 33.  I think
we can make
> this code work for 32-bit smis, on x64.

Smis are sign-extended 32-bit numbers.

http://codereview.chromium.org/125185/diff/1/6#newcode670
Line 670: __ cmpq(rax, Immediate(0xc0000000));
On 2009/06/17 08:27:48, William Hesse wrote:
> cmpl, and many previous instructions should be changed.

Should be cmpq, to get sign extension on the immediate.

http://codereview.chromium.org/125185/diff/1/6#newcode858
Line 858: __ ret(0);
Changed.
Although, somehow, I find ret(0) more readable than Ret(). Guess the
capital letter stands out.

http://codereview.chromium.org/125185

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