Revision: 2594
Author: [email protected]
Date: Fri Jul 31 01:04:41 2009
Log: X64: Add fix of issue 392 to X64
Review URL: http://codereview.chromium.org/160393
http://code.google.com/p/v8/source/detail?r=2594
Modified:
/branches/bleeding_edge/src/x64/codegen-x64.cc
/branches/bleeding_edge/src/x64/disasm-x64.cc
/branches/bleeding_edge/test/mjsunit/mjsunit.status
=======================================
--- /branches/bleeding_edge/src/x64/codegen-x64.cc Thu Jul 30 05:09:51 2009
+++ /branches/bleeding_edge/src/x64/codegen-x64.cc Fri Jul 31 01:04:41 2009
@@ -5555,13 +5555,16 @@
ASSERT(slot != NULL);
if (slot->type() == Slot::LOOKUP ||
slot->type() == Slot::CONTEXT ||
- slot->var()->mode() == Variable::CONST) {
+ slot->var()->mode() == Variable::CONST ||
+ slot->is_arguments()) {
GetValue(typeof_state);
return;
}
// Only non-constant, frame-allocated parameters and locals can reach
- // here.
+ // here. Be careful not to use the optimizations for arguments
+ // object access since it may not have been initialized yet.
+ ASSERT(!slot->is_arguments());
if (slot->type() == Slot::PARAMETER) {
cgen_->frame()->TakeParameterAt(slot->index());
} else {
=======================================
--- /branches/bleeding_edge/src/x64/disasm-x64.cc Mon Jul 27 11:51:46 2009
+++ /branches/bleeding_edge/src/x64/disasm-x64.cc Fri Jul 31 01:04:41 2009
@@ -139,7 +139,7 @@
static const char* conditional_code_suffix[] = {
- "o", "no", "c", "nc", "z", "nz", "a", "na",
+ "o", "no", "c", "nc", "z", "nz", "na", "a",
"s", "ns", "pe", "po", "l", "ge", "le", "g"
};
@@ -252,6 +252,24 @@
static InstructionTable instruction_table;
+static InstructionDesc cmov_instructions[16] = {
+ {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
+ {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
+};
//------------------------------------------------------------------------------
// DisassemblerX64 implementation.
@@ -533,7 +551,7 @@
value = 0; // Initialize variables on all paths to satisfy the
compiler.
count = 0;
}
- AppendToBuffer(V8_PTR_PREFIX"x", value);
+ AppendToBuffer("%" V8_PTR_PREFIX "x", value);
return count;
}
@@ -966,6 +984,13 @@
// RDTSC or CPUID
AppendToBuffer("%s", mnemonic);
+ } else if ((opcode & 0xF0) == 0x40) {
+ // CMOVcc: conditional move.
+ int condition = opcode & 0x0F;
+ const InstructionDesc& idesc = cmov_instructions[condition];
+ byte_size_operand_ = idesc.byte_size_operation;
+ current += PrintOperands(idesc.mnem, idesc.op_order_, current);
+
} else if ((opcode & 0xF0) == 0x80) {
// Jcc: Conditional jump (branch).
current = data + JumpConditional(data);
@@ -1350,9 +1375,9 @@
const char* memory_location = NameOfAddress(
reinterpret_cast<byte*>(
*reinterpret_cast<int32_t*>(data + 1)));
- if (*data == 0xA3) { // Opcode 0xA3
+ if (*data == 0xA1) { // Opcode 0xA1
AppendToBuffer("movzxlq rax,(%s)", memory_location);
- } else { // Opcode 0xA1
+ } else { // Opcode 0xA3
AppendToBuffer("movzxlq (%s),rax", memory_location);
}
data += 5;
@@ -1362,9 +1387,9 @@
// New x64 instruction mov rax,(imm_64).
const char* memory_location = NameOfAddress(
*reinterpret_cast<byte**>(data + 1));
- if (*data == 0xA3) { // Opcode 0xA3
+ if (*data == 0xA1) { // Opcode 0xA1
AppendToBuffer("movq rax,(%s)", memory_location);
- } else { // Opcode 0xA1
+ } else { // Opcode 0xA3
AppendToBuffer("movq (%s),rax", memory_location);
}
data += 9;
=======================================
--- /branches/bleeding_edge/test/mjsunit/mjsunit.status Thu Jul 30 00:31:54
2009
+++ /branches/bleeding_edge/test/mjsunit/mjsunit.status Fri Jul 31 01:04:41
2009
@@ -101,7 +101,6 @@
debug-handle: CRASH || FAIL
debug-clearbreakpointgroup: CRASH || FAIL
regress/regress-269: CRASH || FAIL
-regress/regress-392: CRASH || FAIL
regress/regress-1200351: CRASH || FAIL
regress/regress-998565: CRASH || FAIL
tools/tickprocessor: PASS || CRASH || FAIL
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