Reviewers: ulan, jochen,
Description:
ARM64: Generate better immediates for shifted ops
Improve code generated for immediate data processing operations where the
shift
on the operation can be exploited to use fewer instructions for the
immediate.
For example, Add(x0, x0, 0x1f7de) used to generate:
movz x16, 0xf7de
movk x16, 0x1, lsl #16
add x0, x0, x16
now generates:
movz x16, 0xfbef
add x0, x0, x16, lsl #1
BUG=
Please review this at https://codereview.chromium.org/368313002/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+92, -23 lines):
M src/arm64/macro-assembler-arm64.h
M src/arm64/macro-assembler-arm64.cc
M src/arm64/macro-assembler-arm64-inl.h
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