Revision: 22778
Author: [email protected]
Date: Fri Aug 1 07:42:06 2014 UTC
Log: X87: Land the Fan (disabled)
port r22709.
This patch only covers the code change of orginal X87 port.
For the changes under ./src/compiler/ and ./tools/gyp/v8.gyp file,
I will submit it in another seperate patch.
BUG=
[email protected]
Review URL: https://codereview.chromium.org/430423002
Patch from Chunyang Dai <[email protected]>.
http://code.google.com/p/v8/source/detail?r=22778
Modified:
/branches/bleeding_edge/src/x87/assembler-x87-inl.h
/branches/bleeding_edge/src/x87/assembler-x87.cc
/branches/bleeding_edge/src/x87/assembler-x87.h
/branches/bleeding_edge/src/x87/code-stubs-x87.cc
/branches/bleeding_edge/src/x87/disasm-x87.cc
/branches/bleeding_edge/src/x87/lithium-x87.cc
/branches/bleeding_edge/src/x87/lithium-x87.h
/branches/bleeding_edge/test/cctest/test-assembler-x87.cc
/branches/bleeding_edge/test/cctest/test-disasm-x87.cc
=======================================
--- /branches/bleeding_edge/src/x87/assembler-x87-inl.h Tue Jul 15 10:51:12
2014 UTC
+++ /branches/bleeding_edge/src/x87/assembler-x87-inl.h Fri Aug 1 07:42:06
2014 UTC
@@ -555,6 +555,12 @@
set_dispr(disp, rmode);
}
+
+Operand::Operand(Immediate imm) {
+ // [disp/r]
+ set_modrm(0, ebp);
+ set_dispr(imm.x_, imm.rmode_);
+}
} } // namespace v8::internal
#endif // V8_X87_ASSEMBLER_X87_INL_H_
=======================================
--- /branches/bleeding_edge/src/x87/assembler-x87.cc Mon Jun 30 15:37:07
2014 UTC
+++ /branches/bleeding_edge/src/x87/assembler-x87.cc Fri Aug 1 07:42:06
2014 UTC
@@ -565,6 +565,13 @@
EMIT(0xC0 | src.code() << 3 | dst.code());
}
}
+
+
+void Assembler::xchg(Register dst, const Operand& src) {
+ EnsureSpace ensure_space(this);
+ EMIT(0x87);
+ emit_operand(dst, src);
+}
void Assembler::adc(Register dst, int32_t imm32) {
@@ -750,10 +757,17 @@
}
-void Assembler::idiv(Register src) {
+void Assembler::idiv(const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0xF7);
- EMIT(0xF8 | src.code());
+ emit_operand(edi, src);
+}
+
+
+void Assembler::div(const Operand& src) {
+ EnsureSpace ensure_space(this);
+ EMIT(0xF7);
+ emit_operand(esi, src);
}
@@ -773,14 +787,19 @@
void Assembler::imul(Register dst, Register src, int32_t imm32) {
+ imul(dst, Operand(src), imm32);
+}
+
+
+void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
EnsureSpace ensure_space(this);
if (is_int8(imm32)) {
EMIT(0x6B);
- EMIT(0xC0 | dst.code() << 3 | src.code());
+ emit_operand(dst, src);
EMIT(imm32);
} else {
EMIT(0x69);
- EMIT(0xC0 | dst.code() << 3 | src.code());
+ emit_operand(dst, src);
emit(imm32);
}
}
@@ -818,6 +837,13 @@
EMIT(0xF7);
EMIT(0xD8 | dst.code());
}
+
+
+void Assembler::neg(const Operand& dst) {
+ EnsureSpace ensure_space(this);
+ EMIT(0xF7);
+ emit_operand(ebx, dst);
+}
void Assembler::not_(Register dst) {
@@ -825,6 +851,13 @@
EMIT(0xF7);
EMIT(0xD0 | dst.code());
}
+
+
+void Assembler::not_(const Operand& dst) {
+ EnsureSpace ensure_space(this);
+ EMIT(0xF7);
+ emit_operand(edx, dst);
+}
void Assembler::or_(Register dst, int32_t imm32) {
@@ -902,24 +935,24 @@
}
-void Assembler::sar(Register dst, uint8_t imm8) {
+void Assembler::sar(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
ASSERT(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
- EMIT(0xF8 | dst.code());
+ emit_operand(edi, dst);
} else {
EMIT(0xC1);
- EMIT(0xF8 | dst.code());
+ emit_operand(edi, dst);
EMIT(imm8);
}
}
-void Assembler::sar_cl(Register dst) {
+void Assembler::sar_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
- EMIT(0xF8 | dst.code());
+ emit_operand(edi, dst);
}
@@ -938,24 +971,24 @@
}
-void Assembler::shl(Register dst, uint8_t imm8) {
+void Assembler::shl(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
ASSERT(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
- EMIT(0xE0 | dst.code());
+ emit_operand(esp, dst);
} else {
EMIT(0xC1);
- EMIT(0xE0 | dst.code());
+ emit_operand(esp, dst);
EMIT(imm8);
}
}
-void Assembler::shl_cl(Register dst) {
+void Assembler::shl_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
- EMIT(0xE0 | dst.code());
+ emit_operand(esp, dst);
}
@@ -967,24 +1000,24 @@
}
-void Assembler::shr(Register dst, uint8_t imm8) {
+void Assembler::shr(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
ASSERT(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
- EMIT(0xE8 | dst.code());
+ emit_operand(ebp, dst);
} else {
EMIT(0xC1);
- EMIT(0xE8 | dst.code());
+ emit_operand(ebp, dst);
EMIT(imm8);
}
}
-void Assembler::shr_cl(Register dst) {
+void Assembler::shr_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
- EMIT(0xE8 | dst.code());
+ emit_operand(ebp, dst);
}
=======================================
--- /branches/bleeding_edge/src/x87/assembler-x87.h Thu Jun 5 08:33:42
2014 UTC
+++ /branches/bleeding_edge/src/x87/assembler-x87.h Fri Aug 1 07:42:06
2014 UTC
@@ -292,6 +292,7 @@
int x_;
RelocInfo::Mode rmode_;
+ friend class Operand;
friend class Assembler;
friend class MacroAssembler;
};
@@ -314,9 +315,14 @@
class Operand BASE_EMBEDDED {
public:
+ // reg
+ INLINE(explicit Operand(Register reg));
+
// [disp/r]
INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
- // disp only must always be relocated
+
+ // [disp/r]
+ INLINE(explicit Operand(Immediate imm));
// [base + disp/r]
explicit Operand(Register base, int32_t disp,
@@ -352,6 +358,10 @@
return Operand(reinterpret_cast<int32_t>(cell.location()),
RelocInfo::CELL);
}
+
+ static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
+ return Operand(base, imm.x_, imm.rmode_);
+ }
// Returns true if this Operand is a wrapper for the specified register.
bool is_reg(Register reg) const;
@@ -364,9 +374,6 @@
Register reg() const;
private:
- // reg
- INLINE(explicit Operand(Register reg));
-
// Set the ModRM byte without an encoded 'reg' register. The
// register is encoded later as part of the emit_operand operation.
inline void set_modrm(int mod, Register rm);
@@ -383,7 +390,6 @@
friend class Assembler;
friend class MacroAssembler;
- friend class LCodeGen;
};
@@ -630,8 +636,9 @@
void rep_stos();
void stos();
- // Exchange two registers
+ // Exchange
void xchg(Register dst, Register src);
+ void xchg(Register dst, const Operand& src);
// Arithmetics
void adc(Register dst, int32_t imm32);
@@ -673,13 +680,17 @@
void cdq();
- void idiv(Register src);
+ void idiv(Register src) { idiv(Operand(src)); }
+ void idiv(const Operand& src);
+ void div(Register src) { div(Operand(src)); }
+ void div(const Operand& src);
// Signed multiply instructions.
void imul(Register src); // edx:eax = eax
* src.
void imul(Register dst, Register src) { imul(dst, Operand(src)); }
void imul(Register dst, const Operand& src); // dst = dst *
src.
void imul(Register dst, Register src, int32_t imm32); // dst = src *
imm32.
+ void imul(Register dst, const Operand& src, int32_t imm32);
void inc(Register dst);
void inc(const Operand& dst);
@@ -690,8 +701,10 @@
void mul(Register src); // edx:eax = eax
* reg.
void neg(Register dst);
+ void neg(const Operand& dst);
void not_(Register dst);
+ void not_(const Operand& dst);
void or_(Register dst, int32_t imm32);
void or_(Register dst, Register src) { or_(dst, Operand(src)); }
@@ -705,22 +718,28 @@
void ror(Register dst, uint8_t imm8);
void ror_cl(Register dst);
- void sar(Register dst, uint8_t imm8);
- void sar_cl(Register dst);
+ void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
+ void sar(const Operand& dst, uint8_t imm8);
+ void sar_cl(Register dst) { sar_cl(Operand(dst)); }
+ void sar_cl(const Operand& dst);
void sbb(Register dst, const Operand& src);
void shld(Register dst, Register src) { shld(dst, Operand(src)); }
void shld(Register dst, const Operand& src);
- void shl(Register dst, uint8_t imm8);
- void shl_cl(Register dst);
+ void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
+ void shl(const Operand& dst, uint8_t imm8);
+ void shl_cl(Register dst) { shl_cl(Operand(dst)); }
+ void shl_cl(const Operand& dst);
void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
void shrd(Register dst, const Operand& src);
- void shr(Register dst, uint8_t imm8);
- void shr_cl(Register dst);
+ void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
+ void shr(const Operand& dst, uint8_t imm8);
+ void shr_cl(Register dst) { shr_cl(Operand(dst)); }
+ void shr_cl(const Operand& dst);
void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
void sub(const Operand& dst, const Immediate& x);
=======================================
--- /branches/bleeding_edge/src/x87/code-stubs-x87.cc Wed Jul 30 13:54:45
2014 UTC
+++ /branches/bleeding_edge/src/x87/code-stubs-x87.cc Fri Aug 1 07:42:06
2014 UTC
@@ -82,6 +82,34 @@
Register registers[] = { esi, ebx, edx };
descriptor->Initialize(MajorKey(), ARRAY_SIZE(registers), registers);
}
+
+
+void InstanceofStub::InitializeInterfaceDescriptor(
+ Isolate* isolate, CodeStubInterfaceDescriptor* descriptor) {
+ Register registers[] = {esi, left(), right()};
+ descriptor->Initialize(MajorKey(), ARRAY_SIZE(registers), registers);
+}
+
+
+void CallFunctionStub::InitializeInterfaceDescriptor(
+ Isolate* isolate, CodeStubInterfaceDescriptor* descriptor) {
+ Register registers[] = {esi, edi};
+ descriptor->Initialize(MajorKey(), ARRAY_SIZE(registers), registers);
+}
+
+
+void CallConstructStub::InitializeInterfaceDescriptor(
+ Isolate* isolate, CodeStubInterfaceDescriptor* descriptor) {
+ // eax : number of arguments
+ // ebx : feedback vector
+ // edx : (only if ebx is not the megamorphic symbol) slot in feedback
+ // vector (Smi)
+ // edi : constructor function
+ // TODO(turbofan): So far we don't gather type feedback and hence skip
the
+ // slot parameter, but ArrayConstructStub needs the vector to be
undefined.
+ Register registers[] = {esi, eax, edi, ebx};
+ descriptor->Initialize(MajorKey(), ARRAY_SIZE(registers), registers);
+}
void RegExpConstructResultStub::InitializeInterfaceDescriptor(
@@ -2446,7 +2474,7 @@
// If there is a call site cache don't look in the global cache, but do
the
// real lookup and update the call site cache.
- if (!HasCallSiteInlineCheck()) {
+ if (!HasCallSiteInlineCheck() && !ReturnTrueFalseObject()) {
// Look up the function and the map in the instanceof cache.
Label miss;
__ CompareRoot(function, scratch,
Heap::kInstanceofCacheFunctionRootIndex);
@@ -2505,6 +2533,9 @@
if (!HasCallSiteInlineCheck()) {
__ mov(eax, Immediate(0));
__ StoreRoot(eax, scratch, Heap::kInstanceofCacheAnswerRootIndex);
+ if (ReturnTrueFalseObject()) {
+ __ mov(eax, factory->true_value());
+ }
} else {
// Get return address and delta to inlined map check.
__ mov(eax, factory->true_value());
@@ -2525,6 +2556,9 @@
if (!HasCallSiteInlineCheck()) {
__ mov(eax, Immediate(Smi::FromInt(1)));
__ StoreRoot(eax, scratch, Heap::kInstanceofCacheAnswerRootIndex);
+ if (ReturnTrueFalseObject()) {
+ __ mov(eax, factory->false_value());
+ }
} else {
// Get return address and delta to inlined map check.
__ mov(eax, factory->false_value());
@@ -2552,20 +2586,32 @@
// Null is not instance of anything.
__ cmp(object, factory->null_value());
__ j(not_equal, &object_not_null, Label::kNear);
- __ Move(eax, Immediate(Smi::FromInt(1)));
+ if (ReturnTrueFalseObject()) {
+ __ mov(eax, factory->false_value());
+ } else {
+ __ Move(eax, Immediate(Smi::FromInt(1)));
+ }
__ ret((HasArgsInRegisters() ? 0 : 2) * kPointerSize);
__ bind(&object_not_null);
// Smi values is not instance of anything.
__ JumpIfNotSmi(object, &object_not_null_or_smi, Label::kNear);
- __ Move(eax, Immediate(Smi::FromInt(1)));
+ if (ReturnTrueFalseObject()) {
+ __ mov(eax, factory->false_value());
+ } else {
+ __ Move(eax, Immediate(Smi::FromInt(1)));
+ }
__ ret((HasArgsInRegisters() ? 0 : 2) * kPointerSize);
__ bind(&object_not_null_or_smi);
// String values is not instance of anything.
Condition is_string = masm->IsObjectStringType(object, scratch, scratch);
__ j(NegateCondition(is_string), &slow, Label::kNear);
- __ Move(eax, Immediate(Smi::FromInt(1)));
+ if (ReturnTrueFalseObject()) {
+ __ mov(eax, factory->false_value());
+ } else {
+ __ Move(eax, Immediate(Smi::FromInt(1)));
+ }
__ ret((HasArgsInRegisters() ? 0 : 2) * kPointerSize);
// Slow-case: Go through the JavaScript implementation.
=======================================
--- /branches/bleeding_edge/src/x87/disasm-x87.cc Fri Jun 20 08:40:11 2014
UTC
+++ /branches/bleeding_edge/src/x87/disasm-x87.cc Fri Aug 1 07:42:06 2014
UTC
@@ -529,77 +529,94 @@
// Returns number of bytes used, including *data.
int DisassemblerX87::F7Instruction(byte* data) {
ASSERT_EQ(0xF7, *data);
- byte modrm = *(data+1);
+ byte modrm = *++data;
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
- if (mod == 3 && regop != 0) {
- const char* mnem = NULL;
- switch (regop) {
- case 2: mnem = "not"; break;
- case 3: mnem = "neg"; break;
- case 4: mnem = "mul"; break;
- case 5: mnem = "imul"; break;
- case 7: mnem = "idiv"; break;
- default: UnimplementedInstruction();
- }
- AppendToBuffer("%s %s", mnem, NameOfCPURegister(rm));
- return 2;
- } else if (mod == 3 && regop == eax) {
- int32_t imm = *reinterpret_cast<int32_t*>(data+2);
- AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
- return 6;
- } else if (regop == eax) {
- AppendToBuffer("test ");
- int count = PrintRightOperand(data+1);
- int32_t imm = *reinterpret_cast<int32_t*>(data+1+count);
- AppendToBuffer(",0x%x", imm);
- return 1+count+4 /*int32_t*/;
- } else {
- UnimplementedInstruction();
- return 2;
+ const char* mnem = NULL;
+ switch (regop) {
+ case 0:
+ mnem = "test";
+ break;
+ case 2:
+ mnem = "not";
+ break;
+ case 3:
+ mnem = "neg";
+ break;
+ case 4:
+ mnem = "mul";
+ break;
+ case 5:
+ mnem = "imul";
+ break;
+ case 6:
+ mnem = "div";
+ break;
+ case 7:
+ mnem = "idiv";
+ break;
+ default:
+ UnimplementedInstruction();
}
+ AppendToBuffer("%s ", mnem);
+ int count = PrintRightOperand(data);
+ if (regop == 0) {
+ AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + count));
+ count += 4;
+ }
+ return 1 + count;
}
int DisassemblerX87::D1D3C1Instruction(byte* data) {
byte op = *data;
ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1);
- byte modrm = *(data+1);
+ byte modrm = *++data;
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
int imm8 = -1;
- int num_bytes = 2;
- if (mod == 3) {
- const char* mnem = NULL;
- switch (regop) {
- case kROL: mnem = "rol"; break;
- case kROR: mnem = "ror"; break;
- case kRCL: mnem = "rcl"; break;
- case kRCR: mnem = "rcr"; break;
- case kSHL: mnem = "shl"; break;
- case KSHR: mnem = "shr"; break;
- case kSAR: mnem = "sar"; break;
- default: UnimplementedInstruction();
- }
- if (op == 0xD1) {
- imm8 = 1;
- } else if (op == 0xC1) {
- imm8 = *(data+2);
- num_bytes = 3;
- } else if (op == 0xD3) {
- // Shift/rotate by cl.
- }
- ASSERT_NE(NULL, mnem);
- AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
- if (imm8 >= 0) {
- AppendToBuffer("%d", imm8);
- } else {
- AppendToBuffer("cl");
- }
+ const char* mnem = NULL;
+ switch (regop) {
+ case kROL:
+ mnem = "rol";
+ break;
+ case kROR:
+ mnem = "ror";
+ break;
+ case kRCL:
+ mnem = "rcl";
+ break;
+ case kRCR:
+ mnem = "rcr";
+ break;
+ case kSHL:
+ mnem = "shl";
+ break;
+ case KSHR:
+ mnem = "shr";
+ break;
+ case kSAR:
+ mnem = "sar";
+ break;
+ default:
+ UnimplementedInstruction();
+ }
+ AppendToBuffer("%s ", mnem);
+ int count = PrintRightOperand(data);
+ if (op == 0xD1) {
+ imm8 = 1;
+ } else if (op == 0xC1) {
+ imm8 = *(data + 2);
+ count++;
+ } else if (op == 0xD3) {
+ // Shift/rotate by cl.
+ }
+ if (imm8 >= 0) {
+ AppendToBuffer(",%d", imm8);
} else {
- UnimplementedInstruction();
+ AppendToBuffer(",cl");
}
- return num_bytes;
+ return 1 + count;
}
@@ -954,17 +971,18 @@
data += 3;
break;
- case 0x69: // fall through
- case 0x6B:
- { int mod, regop, rm;
- get_modrm(*(data+1), &mod, ®op, &rm);
- int32_t imm =
- *data == 0x6B ? *(data+2) :
*reinterpret_cast<int32_t*>(data+2);
- AppendToBuffer("imul %s,%s,0x%x",
- NameOfCPURegister(regop),
- NameOfCPURegister(rm),
- imm);
- data += 2 + (*data == 0x6B ? 1 : 4);
+ case 0x6B: {
+ data++;
+ data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
+ AppendToBuffer(",%d", *data);
+ data++;
+ } break;
+
+ case 0x69: {
+ data++;
+ data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
+ AppendToBuffer(",%d", *reinterpret_cast<int32_t*>(data));
+ data += 4;
}
break;
=======================================
--- /branches/bleeding_edge/src/x87/lithium-x87.cc Wed Jul 30 06:46:25 2014
UTC
+++ /branches/bleeding_edge/src/x87/lithium-x87.cc Fri Aug 1 07:42:06 2014
UTC
@@ -7,9 +7,8 @@
#if V8_TARGET_ARCH_X87
#include "src/hydrogen-osr.h"
-#include "src/lithium-allocator-inl.h"
+#include "src/lithium-inl.h"
#include "src/x87/lithium-codegen-x87.h"
-#include "src/x87/lithium-x87.h"
namespace v8 {
namespace internal {
=======================================
--- /branches/bleeding_edge/src/x87/lithium-x87.h Wed Jul 30 06:46:25 2014
UTC
+++ /branches/bleeding_edge/src/x87/lithium-x87.h Fri Aug 1 07:42:06 2014
UTC
@@ -14,6 +14,10 @@
namespace v8 {
namespace internal {
+namespace compiler {
+class RCodeVisualizer;
+}
+
// Forward declarations.
class LCodeGen;
@@ -202,7 +206,7 @@
enum Opcode {
// Declare a unique enum value for each instruction.
#define DECLARE_OPCODE(type) k##type,
- LITHIUM_CONCRETE_INSTRUCTION_LIST(DECLARE_OPCODE)
+ LITHIUM_CONCRETE_INSTRUCTION_LIST(DECLARE_OPCODE) kAdapter,
kNumberOfInstructions
#undef DECLARE_OPCODE
};
@@ -220,6 +224,9 @@
virtual bool IsGap() const { return false; }
virtual bool IsControl() const { return false; }
+
+ // Try deleting this instruction if possible.
+ virtual bool TryDelete() { return false; }
void set_environment(LEnvironment* env) { environment_ = env; }
LEnvironment* environment() const { return environment_; }
@@ -263,11 +270,12 @@
void VerifyCall();
#endif
+ virtual int InputCount() = 0;
+ virtual LOperand* InputAt(int i) = 0;
+
private:
// Iterator support.
friend class InputIterator;
- virtual int InputCount() = 0;
- virtual LOperand* InputAt(int i) = 0;
friend class TempIterator;
virtual int TempCount() = 0;
=======================================
--- /branches/bleeding_edge/test/cctest/test-assembler-x87.cc Tue Jul 8
05:24:52 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-assembler-x87.cc Fri Aug 1
07:42:06 2014 UTC
@@ -33,6 +33,7 @@
#include "src/disassembler.h"
#include "src/factory.h"
#include "src/macro-assembler.h"
+#include "src/ostreams.h"
#include "src/serialize.h"
#include "test/cctest/cctest.h"
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-x87.cc Tue Jul 8
05:24:52 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-disasm-x87.cc Fri Aug 1
07:42:06 2014 UTC
@@ -168,6 +168,11 @@
__ nop();
__ idiv(edx);
+ __ idiv(Operand(edx, ecx, times_1, 1));
+ __ idiv(Operand(esp, 12));
+ __ div(edx);
+ __ div(Operand(edx, ecx, times_1, 1));
+ __ div(Operand(esp, 12));
__ mul(edx);
__ neg(edx);
__ not_(edx);
@@ -175,7 +180,9 @@
__ imul(edx, Operand(ebx, ecx, times_4, 10000));
__ imul(edx, ecx, 12);
+ __ imul(edx, Operand(edx, eax, times_2, 42), 8);
__ imul(edx, ecx, 1000);
+ __ imul(edx, Operand(ebx, ecx, times_4, 1), 9000);
__ inc(edx);
__ inc(Operand(ebx, ecx, times_4, 10000));
@@ -197,15 +204,24 @@
__ sar(edx, 1);
__ sar(edx, 6);
__ sar_cl(edx);
+ __ sar(Operand(ebx, ecx, times_4, 10000), 1);
+ __ sar(Operand(ebx, ecx, times_4, 10000), 6);
+ __ sar_cl(Operand(ebx, ecx, times_4, 10000));
__ sbb(edx, Operand(ebx, ecx, times_4, 10000));
__ shld(edx, Operand(ebx, ecx, times_4, 10000));
__ shl(edx, 1);
__ shl(edx, 6);
__ shl_cl(edx);
+ __ shl(Operand(ebx, ecx, times_4, 10000), 1);
+ __ shl(Operand(ebx, ecx, times_4, 10000), 6);
+ __ shl_cl(Operand(ebx, ecx, times_4, 10000));
__ shrd(edx, Operand(ebx, ecx, times_4, 10000));
__ shr(edx, 1);
__ shr(edx, 7);
__ shr_cl(edx);
+ __ shr(Operand(ebx, ecx, times_4, 10000), 1);
+ __ shr(Operand(ebx, ecx, times_4, 10000), 6);
+ __ shr_cl(Operand(ebx, ecx, times_4, 10000));
// Immediates
@@ -361,6 +377,14 @@
__ frndint();
__ fninit();
__ nop();
+
+ // xchg.
+ {
+ __ xchg(eax, eax);
+ __ xchg(eax, ebx);
+ __ xchg(ebx, ebx);
+ __ xchg(ebx, Operand(esp, 12));
+ }
// Nop instructions
for (int i = 0; i < 16; i++) {
--
--
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