Revision: 22876
Author: [email protected]
Date: Tue Aug 5 13:26:55 2014 UTC
Log: [turbofan] Improve testability of the InstructionSelector.
Allow to pass the set of supported CPU features to
the InstructionSelector, so it can be tested without
messing with the command line flags.
Also add InstructionSelector sample for ia32.
TEST=cctest/test-instruction-selector,cctest/test-instruction-selector-{arm,ia32}
[email protected]
Review URL: https://codereview.chromium.org/441883004
http://code.google.com/p/v8/source/detail?r=22876
Added:
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector-ia32.cc
Modified:
/branches/bleeding_edge/src/assembler.h
/branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
/branches/bleeding_edge/src/compiler/instruction-selector.cc
/branches/bleeding_edge/src/compiler/instruction-selector.h
/branches/bleeding_edge/test/cctest/cctest.gyp
/branches/bleeding_edge/test/cctest/compiler/instruction-selector-tester.h
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector-arm.cc
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector.cc
=======================================
--- /dev/null
+++
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector-ia32.cc
Tue Aug 5 13:26:55 2014 UTC
@@ -0,0 +1,66 @@
+// Copyright 2014 the V8 project authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+#include "test/cctest/compiler/instruction-selector-tester.h"
+#include "test/cctest/compiler/value-helper.h"
+
+using namespace v8::internal;
+using namespace v8::internal::compiler;
+
+TEST(InstructionSelectorInt32AddP) {
+ InstructionSelectorTester m;
+ m.Return(m.Int32Add(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kIA32Add, m.code[0]->arch_opcode());
+}
+
+
+TEST(InstructionSelectorInt32AddImm) {
+ FOR_INT32_INPUTS(i) {
+ int32_t imm = *i;
+ {
+ InstructionSelectorTester m;
+ m.Return(m.Int32Add(m.Parameter(0), m.Int32Constant(imm)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kIA32Add, m.code[0]->arch_opcode());
+ CHECK_EQ(2, m.code[0]->InputCount());
+ CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
+ }
+ {
+ InstructionSelectorTester m;
+ m.Return(m.Int32Add(m.Int32Constant(imm), m.Parameter(0)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kIA32Add, m.code[0]->arch_opcode());
+ CHECK_EQ(2, m.code[0]->InputCount());
+ CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
+ }
+ }
+}
+
+
+TEST(InstructionSelectorInt32SubP) {
+ InstructionSelectorTester m;
+ m.Return(m.Int32Sub(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kIA32Sub, m.code[0]->arch_opcode());
+ CHECK_EQ(1, m.code[0]->OutputCount());
+}
+
+
+TEST(InstructionSelectorInt32SubImm) {
+ FOR_INT32_INPUTS(i) {
+ int32_t imm = *i;
+ InstructionSelectorTester m;
+ m.Return(m.Int32Sub(m.Parameter(0), m.Int32Constant(imm)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kIA32Sub, m.code[0]->arch_opcode());
+ CHECK_EQ(2, m.code[0]->InputCount());
+ CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
+ }
+}
=======================================
--- /branches/bleeding_edge/src/assembler.h Mon Aug 4 11:34:54 2014 UTC
+++ /branches/bleeding_edge/src/assembler.h Tue Aug 5 13:26:55 2014 UTC
@@ -175,6 +175,11 @@
initialized_ = true;
ProbeImpl(cross_compile);
}
+
+ static unsigned SupportedFeatures() {
+ Probe(false);
+ return supported_;
+ }
static bool IsSupported(CpuFeature f) {
return (supported_ & (1u << f)) != 0;
=======================================
--- /branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
Mon Aug 4 11:34:54 2014 UTC
+++ /branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
Tue Aug 5 13:26:55 2014 UTC
@@ -437,7 +437,7 @@
return;
}
}
- if (CpuFeatures::IsSupported(ARMv7) && m.right().HasValue()) {
+ if (IsSupported(ARMv7) && m.right().HasValue()) {
uint32_t value = m.right().Value();
uint32_t width = CompilerIntrinsics::CountSetBits(value);
uint32_t msb = CompilerIntrinsics::CountLeadingZeros(value);
@@ -525,7 +525,7 @@
void InstructionSelector::VisitWord32Shr(Node* node) {
ArmOperandGenerator g(this);
Int32BinopMatcher m(node);
- if (CpuFeatures::IsSupported(ARMv7) && m.left().IsWord32And() &&
+ if (IsSupported(ARMv7) && m.left().IsWord32And() &&
m.right().IsInRange(0, 31)) {
int32_t lsb = m.right().Value();
Int32BinopMatcher mleft(m.left().node());
@@ -573,7 +573,7 @@
void InstructionSelector::VisitInt32Sub(Node* node) {
ArmOperandGenerator g(this);
Int32BinopMatcher m(node);
- if (CpuFeatures::IsSupported(MLS) && m.right().IsInt32Mul() &&
+ if (IsSupported(MLS) && m.right().IsInt32Mul() &&
CanCover(node, m.right().node())) {
Int32BinopMatcher mright(m.right().node());
Emit(kArmMls, g.DefineAsRegister(node),
g.UseRegister(mright.left().node()),
@@ -615,7 +615,7 @@
InstructionOperand* left_operand,
InstructionOperand* right_operand) {
ArmOperandGenerator g(selector);
- if (CpuFeatures::IsSupported(SUDIV)) {
+ if (selector->IsSupported(SUDIV)) {
selector->Emit(div_opcode, result_operand, left_operand,
right_operand);
return;
}
@@ -662,7 +662,7 @@
InstructionOperand* right_operand = g.UseRegister(m.right().node());
EmitDiv(selector, div_opcode, f64i32_opcode, i32f64_opcode, div_operand,
left_operand, right_operand);
- if (CpuFeatures::IsSupported(MLS)) {
+ if (selector->IsSupported(MLS)) {
selector->Emit(kArmMls, result_operand, div_operand, right_operand,
left_operand);
return;
=======================================
--- /branches/bleeding_edge/src/compiler/instruction-selector.cc Tue Aug 5
11:53:32 2014 UTC
+++ /branches/bleeding_edge/src/compiler/instruction-selector.cc Tue Aug 5
13:26:55 2014 UTC
@@ -14,10 +14,12 @@
namespace compiler {
InstructionSelector::InstructionSelector(InstructionSequence* sequence,
- SourcePositionTable*
source_positions)
+ SourcePositionTable*
source_positions,
+ Features features)
: zone_(sequence->isolate()),
sequence_(sequence),
source_positions_(source_positions),
+ features_(features),
current_block_(NULL),
instructions_(InstructionDeque::allocator_type(zone())),
defined_(graph()->NodeCount(), false,
BoolVector::allocator_type(zone())),
=======================================
--- /branches/bleeding_edge/src/compiler/instruction-selector.h Mon Aug 4
08:18:37 2014 UTC
+++ /branches/bleeding_edge/src/compiler/instruction-selector.h Tue Aug 5
13:26:55 2014 UTC
@@ -22,8 +22,12 @@
class InstructionSelector V8_FINAL {
public:
- explicit InstructionSelector(InstructionSequence* sequence,
- SourcePositionTable* source_positions);
+ // Forward declarations.
+ class Features;
+
+ InstructionSelector(InstructionSequence* sequence,
+ SourcePositionTable* source_positions,
+ Features features = SupportedFeatures());
// Visit code for the entire graph with the included schedule.
void SelectInstructions();
@@ -53,6 +57,32 @@
InstructionOperand** inputs, size_t temp_count = 0,
InstructionOperand* *temps = NULL);
Instruction* Emit(Instruction* instr);
+
+ //
===========================================================================
+ // ============== Architecture-independent CPU feature methods.
==============
+ //
===========================================================================
+
+ class Features V8_FINAL {
+ public:
+ Features() : bits_(0) {}
+ explicit Features(unsigned bits) : bits_(bits) {}
+ explicit Features(CpuFeature f) : bits_(1u << f) {}
+ Features(CpuFeature f1, CpuFeature f2) : bits_((1u << f1) | (1u <<
f2)) {}
+
+ bool Contains(CpuFeature f) const { return (bits_ & (1u << f)); }
+
+ private:
+ unsigned bits_;
+ };
+
+ bool IsSupported(CpuFeature feature) const {
+ return features_.Contains(feature);
+ }
+
+ // Returns the features supported on the target platform.
+ static Features SupportedFeatures() {
+ return Features(CpuFeatures::SupportedFeatures());
+ }
private:
friend class OperandGenerator;
@@ -168,6 +198,7 @@
Zone zone_;
InstructionSequence* sequence_;
SourcePositionTable* source_positions_;
+ Features features_;
BasicBlock* current_block_;
Instructions instructions_;
BoolVector defined_;
=======================================
--- /branches/bleeding_edge/test/cctest/cctest.gyp Fri Aug 1 08:16:19 2014
UTC
+++ /branches/bleeding_edge/test/cctest/cctest.gyp Tue Aug 5 13:26:55 2014
UTC
@@ -171,6 +171,7 @@
'conditions': [
['v8_target_arch=="ia32"', {
'sources': [ ### gcmole(arch:ia32) ###
+ 'compiler/test-instruction-selector-ia32.cc',
'test-assembler-ia32.cc',
'test-code-stubs.cc',
'test-code-stubs-ia32.cc',
=======================================
---
/branches/bleeding_edge/test/cctest/compiler/instruction-selector-tester.h
Wed Jul 30 13:54:45 2014 UTC
+++
/branches/bleeding_edge/test/cctest/compiler/instruction-selector-tester.h
Tue Aug 5 13:26:55 2014 UTC
@@ -36,15 +36,27 @@
return array;
}
- explicit InstructionSelectorTester(Mode mode = kTargetMode)
+ InstructionSelectorTester()
: RawMachineAssembler(
new (main_zone()) Graph(main_zone()), new (main_zone())
MachineCallDescriptorBuilder(kMachineWord32, kParameterCount,
BuildParameterArray(main_zone())),
- MachineOperatorBuilder::pointer_rep()),
- mode_(mode) {}
+ MachineOperatorBuilder::pointer_rep()) {}
+
+ void SelectInstructions(CpuFeature feature) {
+ SelectInstructions(InstructionSelector::Features(feature));
+ }
+
+ void SelectInstructions(CpuFeature feature1, CpuFeature feature2) {
+ SelectInstructions(InstructionSelector::Features(feature1, feature2));
+ }
+
+ void SelectInstructions(Mode mode = kTargetMode) {
+ SelectInstructions(InstructionSelector::Features(), mode);
+ }
- void SelectInstructions() {
+ void SelectInstructions(InstructionSelector::Features features,
+ Mode mode = kTargetMode) {
OFStream out(stdout);
Schedule* schedule = Export();
CHECK_NE(0, graph()->NodeCount());
@@ -52,7 +64,7 @@
Linkage linkage(&info, call_descriptor());
InstructionSequence sequence(&linkage, graph(), schedule);
SourcePositionTable source_positions(graph());
- InstructionSelector selector(&sequence, &source_positions);
+ InstructionSelector selector(&sequence, &source_positions, features);
selector.SelectInstructions();
out << "--- Code sequence after instruction selection --- " << endl
<< sequence;
@@ -60,7 +72,7 @@
i != sequence.end(); ++i) {
Instruction* instr = *i;
if (instr->opcode() < 0) continue;
- if (mode_ == kTargetMode) {
+ if (mode == kTargetMode) {
switch (ArchOpcodeField::decode(instr->opcode())) {
#define CASE(Name) \
case k##Name: \
@@ -98,9 +110,6 @@
VirtualRegisterSet doubles;
VirtualRegisterSet references;
std::deque<Constant> immediates;
-
- private:
- Mode mode_;
};
=======================================
---
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector-arm.cc
Mon Aug 4 08:18:37 2014 UTC
+++
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector-arm.cc
Tue Aug 5 13:26:55 2014 UTC
@@ -117,6 +117,35 @@
CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
}
}
+
+
+TEST(InstructionSelectorDPIImm) {
+ DPIs dpis;
+ Immediates immediates;
+ for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
+ DPI dpi = *i;
+ for (Immediates::const_iterator j = immediates.begin();
+ j != immediates.end(); ++j) {
+ int32_t imm = *j;
+ {
+ InstructionSelectorTester m;
+ m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
+ CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
+ }
+ {
+ InstructionSelectorTester m;
+ m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)));
+ m.SelectInstructions();
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
+ CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
+ }
+ }
+ }
+}
TEST(InstructionSelectorDPIAndShiftP) {
@@ -872,48 +901,12 @@
}
-// The following tests depend on the exact CPU features available, which
we do
-// only fully control in a simulator build.
-#ifdef USE_SIMULATOR
-
-TEST(InstructionSelectorDPIImm_ARMv7AndVFP3Disabled) {
- i::FLAG_enable_armv7 = false;
- i::FLAG_enable_vfp3 = false;
- DPIs dpis;
- Immediates immediates;
- for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
- DPI dpi = *i;
- for (Immediates::const_iterator j = immediates.begin();
- j != immediates.end(); ++j) {
- int32_t imm = *j;
- {
- InstructionSelectorTester m;
- m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)));
- m.SelectInstructions();
- CHECK_EQ(1, m.code.size());
- CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
- CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
- }
- {
- InstructionSelectorTester m;
- m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)));
- m.SelectInstructions();
- CHECK_EQ(1, m.code.size());
- CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
- CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
- }
- }
- }
-}
-
-
-TEST(InstructionSelectorWord32AndImm_ARMv7Enabled) {
- i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32AndImm_ARMv7) {
for (uint32_t width = 1; width <= 32; ++width) {
InstructionSelectorTester m;
m.Return(m.Word32And(m.Parameter(0),
m.Int32Constant(0xffffffffu >> (32 - width))));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
CHECK_EQ(3, m.code[0]->InputCount());
@@ -925,7 +918,7 @@
uint32_t msk = ~((0xffffffffu >> (32 - width)) << lsb);
InstructionSelectorTester m;
m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(msk)));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmBfc, m.code[0]->arch_opcode());
CHECK_EQ(1, m.code[0]->OutputCount());
@@ -939,15 +932,14 @@
}
-TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7Enabled) {
- i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7) {
for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
for (uint32_t width = 1; width <= 32 - lsb; ++width) {
{
InstructionSelectorTester m;
m.Return(m.Word32And(m.Word32Shr(m.Parameter(0),
m.Int32Constant(lsb)),
m.Int32Constant(0xffffffffu >> (32 -
width))));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
CHECK_EQ(3, m.code[0]->InputCount());
@@ -959,7 +951,7 @@
m.Return(
m.Word32And(m.Int32Constant(0xffffffffu >> (32 - width)),
m.Word32Shr(m.Parameter(0),
m.Int32Constant(lsb))));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
CHECK_EQ(3, m.code[0]->InputCount());
@@ -971,8 +963,7 @@
}
-TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7Enabled) {
- i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7) {
for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
for (uint32_t width = 1; width <= 32 - lsb; ++width) {
uint32_t max = 1 << lsb;
@@ -983,7 +974,7 @@
InstructionSelectorTester m;
m.Return(m.Word32Shr(m.Word32And(m.Parameter(0),
m.Int32Constant(msk)),
m.Int32Constant(lsb)));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
CHECK_EQ(3, m.code[0]->InputCount());
@@ -994,7 +985,7 @@
InstructionSelectorTester m;
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk),
m.Parameter(0)),
m.Int32Constant(lsb)));
- m.SelectInstructions();
+ m.SelectInstructions(ARMv7);
CHECK_EQ(1, m.code.size());
CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
CHECK_EQ(3, m.code[0]->InputCount());
@@ -1006,21 +997,9 @@
}
-TEST(InstructionSelectorInt32SubAndInt32MulP_MlsEnabled) {
- i::FLAG_enable_mls = true;
+TEST(InstructionSelectorInt32SubAndInt32MulP) {
InstructionSelectorTester m;
m.Return(
- m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1),
m.Parameter(2))));
- m.SelectInstructions();
- CHECK_EQ(1, m.code.size());
- CHECK_EQ(kArmMls, m.code[0]->arch_opcode());
-}
-
-
-TEST(InstructionSelectorInt32SubAndInt32MulP_MlsDisabled) {
- i::FLAG_enable_mls = false;
- InstructionSelectorTester m;
- m.Return(
m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1),
m.Parameter(2))));
m.SelectInstructions();
CHECK_EQ(2, m.code.size());
@@ -1032,19 +1011,17 @@
}
-TEST(InstructionSelectorInt32DivP_ARMv7AndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32SubAndInt32MulP_MLS) {
InstructionSelectorTester m;
- m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
+ m.Return(
+ m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1),
m.Parameter(2))));
+ m.SelectInstructions(MLS);
CHECK_EQ(1, m.code.size());
- CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
+ CHECK_EQ(kArmMls, m.code[0]->arch_opcode());
}
-TEST(InstructionSelectorInt32DivP_SudivDisabled) {
- i::FLAG_enable_sudiv = false;
+TEST(InstructionSelectorInt32DivP) {
InstructionSelectorTester m;
m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
m.SelectInstructions();
@@ -1064,19 +1041,16 @@
}
-TEST(InstructionSelectorInt32UDivP_ARMv7AndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32DivP_SUDIV) {
InstructionSelectorTester m;
- m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
+ m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(SUDIV);
CHECK_EQ(1, m.code.size());
- CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+ CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
}
-TEST(InstructionSelectorInt32UDivP_SudivDisabled) {
- i::FLAG_enable_sudiv = false;
+TEST(InstructionSelectorInt32UDivP) {
InstructionSelectorTester m;
m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
m.SelectInstructions();
@@ -1096,57 +1070,19 @@
}
-TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_mls = true;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32UDivP_SUDIV) {
InstructionSelectorTester m;
- m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
- CHECK_EQ(2, m.code.size());
- CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
- CHECK_EQ(1, m.code[0]->OutputCount());
- CHECK_EQ(2, m.code[0]->InputCount());
- CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
- CHECK_EQ(1, m.code[1]->OutputCount());
- CHECK_EQ(3, m.code[1]->InputCount());
- CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
- CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
- CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
+ m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(SUDIV);
+ CHECK_EQ(1, m.code.size());
+ CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
}
-TEST(InstructionSelectorInt32ModP_ARMv7AndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_mls = false;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32ModP) {
InstructionSelectorTester m;
m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
m.SelectInstructions();
- CHECK_EQ(3, m.code.size());
- CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
- CHECK_EQ(1, m.code[0]->OutputCount());
- CHECK_EQ(2, m.code[0]->InputCount());
- CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
- CHECK_EQ(1, m.code[1]->OutputCount());
- CHECK_EQ(2, m.code[1]->InputCount());
- CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
- CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
- CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
- CHECK_EQ(1, m.code[2]->OutputCount());
- CHECK_EQ(2, m.code[2]->InputCount());
- CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
- CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
-}
-
-
-TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivDisabled) {
- i::FLAG_enable_armv7 = false;
- i::FLAG_enable_mls = false;
- i::FLAG_enable_sudiv = false;
- InstructionSelectorTester m;
- m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
CHECK_EQ(6, m.code.size());
CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode());
CHECK_EQ(1, m.code[0]->OutputCount());
@@ -1173,54 +1109,45 @@
}
-TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_mls = true;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32ModP_SUDIV) {
InstructionSelectorTester m;
- m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
- CHECK_EQ(2, m.code.size());
- CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+ m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(SUDIV);
+ CHECK_EQ(3, m.code.size());
+ CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
CHECK_EQ(1, m.code[0]->OutputCount());
CHECK_EQ(2, m.code[0]->InputCount());
- CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
+ CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
CHECK_EQ(1, m.code[1]->OutputCount());
- CHECK_EQ(3, m.code[1]->InputCount());
+ CHECK_EQ(2, m.code[1]->InputCount());
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
- CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
+ CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
+ CHECK_EQ(1, m.code[2]->OutputCount());
+ CHECK_EQ(2, m.code[2]->InputCount());
+ CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
+ CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
}
-TEST(InstructionSelectorInt32UModP_ARMv7AndSudivEnabled) {
- i::FLAG_enable_armv7 = true;
- i::FLAG_enable_mls = false;
- i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32ModP_MLS_SUDIV) {
InstructionSelectorTester m;
- m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
- m.SelectInstructions();
- CHECK_EQ(3, m.code.size());
- CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+ m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(MLS, SUDIV);
+ CHECK_EQ(2, m.code.size());
+ CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
CHECK_EQ(1, m.code[0]->OutputCount());
CHECK_EQ(2, m.code[0]->InputCount());
- CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
+ CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
CHECK_EQ(1, m.code[1]->OutputCount());
- CHECK_EQ(2, m.code[1]->InputCount());
+ CHECK_EQ(3, m.code[1]->InputCount());
CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
- CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
- CHECK_EQ(1, m.code[2]->OutputCount());
- CHECK_EQ(2, m.code[2]->InputCount());
- CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
- CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
+ CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
}
-TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivDisabled) {
- i::FLAG_enable_armv7 = false;
- i::FLAG_enable_mls = false;
- i::FLAG_enable_sudiv = false;
+TEST(InstructionSelectorInt32UModP) {
InstructionSelectorTester m;
m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
m.SelectInstructions();
@@ -1249,7 +1176,43 @@
CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1));
}
-#endif // USE_SIMULATOR
+
+TEST(InstructionSelectorInt32UModP_SUDIV) {
+ InstructionSelectorTester m;
+ m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(SUDIV);
+ CHECK_EQ(3, m.code.size());
+ CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+ CHECK_EQ(1, m.code[0]->OutputCount());
+ CHECK_EQ(2, m.code[0]->InputCount());
+ CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
+ CHECK_EQ(1, m.code[1]->OutputCount());
+ CHECK_EQ(2, m.code[1]->InputCount());
+ CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
+ CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
+ CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
+ CHECK_EQ(1, m.code[2]->OutputCount());
+ CHECK_EQ(2, m.code[2]->InputCount());
+ CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
+ CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
+}
+
+
+TEST(InstructionSelectorInt32UModP_MLS_SUDIV) {
+ InstructionSelectorTester m;
+ m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+ m.SelectInstructions(MLS, SUDIV);
+ CHECK_EQ(2, m.code.size());
+ CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+ CHECK_EQ(1, m.code[0]->OutputCount());
+ CHECK_EQ(2, m.code[0]->InputCount());
+ CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
+ CHECK_EQ(1, m.code[1]->OutputCount());
+ CHECK_EQ(3, m.code[1]->InputCount());
+ CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
+ CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
+ CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
+}
TEST(InstructionSelectorWord32EqualP) {
=======================================
---
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector.cc
Thu Jul 31 11:59:49 2014 UTC
+++
/branches/bleeding_edge/test/cctest/compiler/test-instruction-selector.cc
Tue Aug 5 13:26:55 2014 UTC
@@ -7,16 +7,16 @@
using namespace v8::internal;
using namespace v8::internal::compiler;
-#if V8_TURBOFAN_TARGET
+#if V8_TURBOFAN_BACKEND
TEST(InstructionSelectionReturnZero) {
- InstructionSelectorTester m(InstructionSelectorTester::kInternalMode);
+ InstructionSelectorTester m;
m.Return(m.Int32Constant(0));
- m.SelectInstructions();
+ m.SelectInstructions(InstructionSelectorTester::kInternalMode);
CHECK_EQ(2, static_cast<int>(m.code.size()));
CHECK_EQ(kArchNop, m.code[0]->opcode());
CHECK_EQ(kArchRet, m.code[1]->opcode());
CHECK_EQ(1, static_cast<int>(m.code[1]->InputCount()));
}
-#endif
+#endif // !V8_TURBOFAN_BACKEND
--
--
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