Revision: 23387
Author: [email protected]
Date: Tue Aug 26 08:30:18 2014 UTC
Log: [turbofan] Get rid of DefineAsDoubleRegister() and friends.
TEST=compiler-unittests,cctest,mjsunit
[email protected]
Review URL: https://codereview.chromium.org/470623010
https://code.google.com/p/v8/source/detail?r=23387
Modified:
/branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
/branches/bleeding_edge/src/compiler/arm64/instruction-selector-arm64.cc
/branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
/branches/bleeding_edge/src/compiler/instruction-selector-impl.h
/branches/bleeding_edge/src/compiler/instruction-selector.cc
/branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
=======================================
--- /branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
Tue Aug 26 08:29:12 2014 UTC
+++ /branches/bleeding_edge/src/compiler/arm/instruction-selector-arm.cc
Tue Aug 26 08:30:18 2014 UTC
@@ -120,9 +120,9 @@
static void VisitRRRFloat64(InstructionSelector* selector, ArchOpcode
opcode,
Node* node) {
ArmOperandGenerator g(selector);
- selector->Emit(opcode, g.DefineAsDoubleRegister(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ selector->Emit(opcode, g.DefineAsRegister(node),
+ g.UseRegister(node->InputAt(0)),
+ g.UseRegister(node->InputAt(1)));
}
@@ -296,10 +296,6 @@
Node* base = node->InputAt(0);
Node* index = node->InputAt(1);
- InstructionOperand* result = (rep == kRepFloat32 || rep == kRepFloat64)
- ? g.DefineAsDoubleRegister(node)
- : g.DefineAsRegister(node);
-
ArchOpcode opcode;
switch (rep) {
case kRepFloat32:
@@ -325,11 +321,11 @@
}
if (g.CanBeImmediate(index, opcode)) {
- Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), result,
- g.UseRegister(base), g.UseImmediate(index));
+ Emit(opcode | AddressingModeField::encode(kMode_Offset_RI),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseImmediate(index));
} else {
- Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), result,
- g.UseRegister(base), g.UseRegister(index));
+ Emit(opcode | AddressingModeField::encode(kMode_Offset_RR),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseRegister(index));
}
}
@@ -354,9 +350,6 @@
return;
}
DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
- InstructionOperand* val = (rep == kRepFloat32 || rep == kRepFloat64)
- ? g.UseDoubleRegister(value)
- : g.UseRegister(value);
ArchOpcode opcode;
switch (rep) {
@@ -384,10 +377,10 @@
if (g.CanBeImmediate(index, opcode)) {
Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), NULL,
- g.UseRegister(base), g.UseImmediate(index), val);
+ g.UseRegister(base), g.UseImmediate(index), g.UseRegister(value));
} else {
Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), NULL,
- g.UseRegister(base), g.UseRegister(index), val);
+ g.UseRegister(base), g.UseRegister(index), g.UseRegister(value));
}
}
@@ -700,14 +693,14 @@
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
ArmOperandGenerator g(this);
- Emit(kArmVcvtF64S32, g.DefineAsDoubleRegister(node),
+ Emit(kArmVcvtF64S32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
ArmOperandGenerator g(this);
- Emit(kArmVcvtF64U32, g.DefineAsDoubleRegister(node),
+ Emit(kArmVcvtF64U32, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
@@ -715,14 +708,14 @@
void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmVcvtS32F64, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmVcvtU32F64, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
@@ -765,8 +758,7 @@
ArmOperandGenerator g(this);
Float64BinopMatcher m(node);
if (m.right().Is(-1.0)) {
- Emit(kArmVnegF64, g.DefineAsRegister(node),
- g.UseDoubleRegister(m.left().node()));
+ Emit(kArmVnegF64, g.DefineAsRegister(node),
g.UseRegister(m.left().node()));
} else {
VisitRRRFloat64(this, kArmVmulF64, node);
}
@@ -780,9 +772,8 @@
void InstructionSelector::VisitFloat64Mod(Node* node) {
ArmOperandGenerator g(this);
- Emit(kArmVmodF64, g.DefineAsFixedDouble(node, d0),
- g.UseFixedDouble(node->InputAt(0), d0),
- g.UseFixedDouble(node->InputAt(1), d1))->MarkAsCall();
+ Emit(kArmVmodF64, g.DefineAsFixed(node, d0),
g.UseFixed(node->InputAt(0), d0),
+ g.UseFixed(node->InputAt(1), d1))->MarkAsCall();
}
@@ -957,14 +948,13 @@
ArmOperandGenerator g(this);
Float64BinopMatcher m(node);
if (cont->IsBranch()) {
- Emit(cont->Encode(kArmVcmpF64), NULL,
g.UseDoubleRegister(m.left().node()),
- g.UseDoubleRegister(m.right().node()),
g.Label(cont->true_block()),
+ Emit(cont->Encode(kArmVcmpF64), NULL, g.UseRegister(m.left().node()),
+ g.UseRegister(m.right().node()), g.Label(cont->true_block()),
g.Label(cont->false_block()))->MarkAsControl();
} else {
DCHECK(cont->IsSet());
Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
- g.UseDoubleRegister(m.left().node()),
- g.UseDoubleRegister(m.right().node()));
+ g.UseRegister(m.left().node()), g.UseRegister(m.right().node()));
}
}
=======================================
---
/branches/bleeding_edge/src/compiler/arm64/instruction-selector-arm64.cc
Tue Aug 26 08:29:12 2014 UTC
+++
/branches/bleeding_edge/src/compiler/arm64/instruction-selector-arm64.cc
Tue Aug 26 08:30:18 2014 UTC
@@ -83,9 +83,9 @@
static void VisitRRRFloat64(InstructionSelector* selector, ArchOpcode
opcode,
Node* node) {
Arm64OperandGenerator g(selector);
- selector->Emit(opcode, g.DefineAsDoubleRegister(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ selector->Emit(opcode, g.DefineAsRegister(node),
+ g.UseRegister(node->InputAt(0)),
+ g.UseRegister(node->InputAt(1)));
}
@@ -147,13 +147,7 @@
Arm64OperandGenerator g(this);
Node* base = node->InputAt(0);
Node* index = node->InputAt(1);
-
- InstructionOperand* result = (rep == kRepFloat32 || rep == kRepFloat64)
- ? g.DefineAsDoubleRegister(node)
- : g.DefineAsRegister(node);
-
ArchOpcode opcode;
- // TODO(titzer): signed/unsigned small loads
switch (rep) {
case kRepFloat32:
opcode = kArm64LdrS;
@@ -180,11 +174,11 @@
return;
}
if (g.CanBeImmediate(index, kLoadStoreImm)) {
- Emit(opcode | AddressingModeField::encode(kMode_MRI), result,
- g.UseRegister(base), g.UseImmediate(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MRI),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseImmediate(index));
} else {
- Emit(opcode | AddressingModeField::encode(kMode_MRR), result,
- g.UseRegister(base), g.UseRegister(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MRR),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseRegister(index));
}
}
@@ -209,12 +203,6 @@
return;
}
DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
- InstructionOperand* val;
- if (rep == kRepFloat32 || rep == kRepFloat64) {
- val = g.UseDoubleRegister(value);
- } else {
- val = g.UseRegister(value);
- }
ArchOpcode opcode;
switch (rep) {
case kRepFloat32:
@@ -243,10 +231,10 @@
}
if (g.CanBeImmediate(index, kLoadStoreImm)) {
Emit(opcode | AddressingModeField::encode(kMode_MRI), NULL,
- g.UseRegister(base), g.UseImmediate(index), val);
+ g.UseRegister(base), g.UseImmediate(index), g.UseRegister(value));
} else {
Emit(opcode | AddressingModeField::encode(kMode_MRR), NULL,
- g.UseRegister(base), g.UseRegister(index), val);
+ g.UseRegister(base), g.UseRegister(index), g.UseRegister(value));
}
}
@@ -421,14 +409,14 @@
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
Arm64OperandGenerator g(this);
- Emit(kArm64Int32ToFloat64, g.DefineAsDoubleRegister(node),
+ Emit(kArm64Int32ToFloat64, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
Arm64OperandGenerator g(this);
- Emit(kArm64Uint32ToFloat64, g.DefineAsDoubleRegister(node),
+ Emit(kArm64Uint32ToFloat64, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
@@ -436,14 +424,14 @@
void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
Arm64OperandGenerator g(this);
Emit(kArm64Float64ToInt32, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
Arm64OperandGenerator g(this);
Emit(kArm64Float64ToUint32, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
@@ -487,9 +475,9 @@
void InstructionSelector::VisitFloat64Mod(Node* node) {
Arm64OperandGenerator g(this);
- Emit(kArm64Float64Mod, g.DefineAsFixedDouble(node, d0),
- g.UseFixedDouble(node->InputAt(0), d0),
- g.UseFixedDouble(node->InputAt(1), d1))->MarkAsCall();
+ Emit(kArm64Float64Mod, g.DefineAsFixed(node, d0),
+ g.UseFixed(node->InputAt(0), d0),
+ g.UseFixed(node->InputAt(1), d1))->MarkAsCall();
}
@@ -588,8 +576,8 @@
Arm64OperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
- VisitCompare(this, kArm64Float64Cmp, g.UseDoubleRegister(left),
- g.UseDoubleRegister(right), cont);
+ VisitCompare(this, kArm64Float64Cmp, g.UseRegister(left),
+ g.UseRegister(right), cont);
}
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Tue Aug 26 08:29:12 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Tue Aug 26 08:30:18 2014 UTC
@@ -47,9 +47,6 @@
Node* base = node->InputAt(0);
Node* index = node->InputAt(1);
- InstructionOperand* output = (rep == kRepFloat32 || rep == kRepFloat64)
- ? g.DefineAsDoubleRegister(node)
- : g.DefineAsRegister(node);
ArchOpcode opcode;
// TODO(titzer): signed/unsigned small loads
switch (rep) {
@@ -76,18 +73,19 @@
}
if (g.CanBeImmediate(base)) {
if (Int32Matcher(index).Is(0)) { // load [#base + #0]
- Emit(opcode | AddressingModeField::encode(kMode_MI), output,
+ Emit(opcode | AddressingModeField::encode(kMode_MI),
+ g.DefineAsRegister(node), g.UseImmediate(base));
+ } else { // load [#base + %index]
+ Emit(opcode | AddressingModeField::encode(kMode_MRI),
+ g.DefineAsRegister(node), g.UseRegister(index),
g.UseImmediate(base));
- } else { // load [#base + %index]
- Emit(opcode | AddressingModeField::encode(kMode_MRI), output,
- g.UseRegister(index), g.UseImmediate(base));
}
} else if (g.CanBeImmediate(index)) { // load [%base + #index]
- Emit(opcode | AddressingModeField::encode(kMode_MRI), output,
- g.UseRegister(base), g.UseImmediate(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MRI),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseImmediate(index));
} else { // load [%base + %index + K]
- Emit(opcode | AddressingModeField::encode(kMode_MR1I), output,
- g.UseRegister(base), g.UseRegister(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MR1I),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseRegister(index));
}
// TODO(turbofan): addressing modes [r+r*{2,4,8}+K]
}
@@ -114,16 +112,12 @@
}
DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
InstructionOperand* val;
- if (rep == kRepFloat32 || rep == kRepFloat64) {
- val = g.UseDoubleRegister(value);
+ if (g.CanBeImmediate(value)) {
+ val = g.UseImmediate(value);
+ } else if (rep == kRepWord8 || rep == kRepBit) {
+ val = g.UseByteRegister(value);
} else {
- if (g.CanBeImmediate(value)) {
- val = g.UseImmediate(value);
- } else if (rep == kRepWord8 || rep == kRepBit) {
- val = g.UseByteRegister(value);
- } else {
- val = g.UseRegister(value);
- }
+ val = g.UseRegister(value);
}
ArchOpcode opcode;
switch (rep) {
@@ -362,15 +356,14 @@
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
IA32OperandGenerator g(this);
- Emit(kSSEInt32ToFloat64, g.DefineAsDoubleRegister(node),
- g.Use(node->InputAt(0)));
+ Emit(kSSEInt32ToFloat64, g.DefineAsRegister(node),
g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
IA32OperandGenerator g(this);
// TODO(turbofan): IA32 SSE LoadUint32() should take an operand.
- Emit(kSSEUint32ToFloat64, g.DefineAsDoubleRegister(node),
+ Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
@@ -385,39 +378,35 @@
IA32OperandGenerator g(this);
// TODO(turbofan): IA32 SSE subsd() should take an operand.
Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitFloat64Add(Node* node) {
IA32OperandGenerator g(this);
Emit(kSSEFloat64Add, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Sub(Node* node) {
IA32OperandGenerator g(this);
Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Mul(Node* node) {
IA32OperandGenerator g(this);
Emit(kSSEFloat64Mul, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Div(Node* node) {
IA32OperandGenerator g(this);
Emit(kSSEFloat64Div, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
@@ -425,8 +414,8 @@
IA32OperandGenerator g(this);
InstructionOperand* temps[] = {g.TempRegister(eax)};
Emit(kSSEFloat64Mod, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)), 1, temps);
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), 1,
+ temps);
}
@@ -508,8 +497,7 @@
IA32OperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
- VisitCompare(this, kSSEFloat64Cmp, g.UseDoubleRegister(left),
g.Use(right),
- cont);
+ VisitCompare(this, kSSEFloat64Cmp, g.UseRegister(left), g.Use(right),
cont);
}
=======================================
--- /branches/bleeding_edge/src/compiler/instruction-selector-impl.h Thu
Aug 21 11:56:46 2014 UTC
+++ /branches/bleeding_edge/src/compiler/instruction-selector-impl.h Tue
Aug 26 08:30:18 2014 UTC
@@ -24,11 +24,6 @@
return Define(node, new (zone())
UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER));
}
-
- InstructionOperand* DefineAsDoubleRegister(Node* node) {
- return Define(node, new (zone())
-
UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER));
- }
InstructionOperand* DefineSameAsFirst(Node* result) {
return Define(result, new (zone())
@@ -41,7 +36,7 @@
Register::ToAllocationIndex(reg)));
}
- InstructionOperand* DefineAsFixedDouble(Node* node, DoubleRegister reg) {
+ InstructionOperand* DefineAsFixed(Node* node, DoubleRegister reg) {
return Define(node, new (zone())
UnallocatedOperand(UnallocatedOperand::FIXED_DOUBLE_REGISTER,
DoubleRegister::ToAllocationIndex(reg)));
@@ -68,12 +63,6 @@
UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER,
UnallocatedOperand::USED_AT_START));
}
-
- InstructionOperand* UseDoubleRegister(Node* node) {
- return Use(node, new (zone())
- UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER,
- UnallocatedOperand::USED_AT_START));
- }
// Use register or operand for the node. If a register is chosen, it
won't
// alias any temporary or output registers.
@@ -87,13 +76,6 @@
return Use(node, new (zone())
UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER));
}
-
- // Use a unique double register for the node that does not alias any
temporary
- // or output double registers.
- InstructionOperand* UseUniqueDoubleRegister(Node* node) {
- return Use(node, new (zone())
- UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER));
- }
InstructionOperand* UseFixed(Node* node, Register reg) {
return Use(node, new (zone())
@@ -101,7 +83,7 @@
Register::ToAllocationIndex(reg)));
}
- InstructionOperand* UseFixedDouble(Node* node, DoubleRegister reg) {
+ InstructionOperand* UseFixed(Node* node, DoubleRegister reg) {
return Use(node, new (zone())
UnallocatedOperand(UnallocatedOperand::FIXED_DOUBLE_REGISTER,
DoubleRegister::ToAllocationIndex(reg)));
=======================================
--- /branches/bleeding_edge/src/compiler/instruction-selector.cc Tue Aug 26
08:29:12 2014 UTC
+++ /branches/bleeding_edge/src/compiler/instruction-selector.cc Tue Aug 26
08:30:18 2014 UTC
@@ -737,7 +737,7 @@
void InstructionSelector::VisitTruncateFloat64ToInt32(Node* node) {
OperandGenerator g(this);
Emit(kArchTruncateDoubleToI, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
=======================================
--- /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Tue Aug 26 08:29:12 2014 UTC
+++ /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Tue Aug 26 08:30:18 2014 UTC
@@ -62,9 +62,6 @@
Node* base = node->InputAt(0);
Node* index = node->InputAt(1);
- InstructionOperand* output = (rep == kRepFloat32 || rep == kRepFloat64)
- ? g.DefineAsDoubleRegister(node)
- : g.DefineAsRegister(node);
ArchOpcode opcode;
// TODO(titzer): signed/unsigned small loads
switch (rep) {
@@ -94,14 +91,14 @@
}
if (g.CanBeImmediate(base)) {
// load [#base + %index]
- Emit(opcode | AddressingModeField::encode(kMode_MRI), output,
- g.UseRegister(index), g.UseImmediate(base));
+ Emit(opcode | AddressingModeField::encode(kMode_MRI),
+ g.DefineAsRegister(node), g.UseRegister(index),
g.UseImmediate(base));
} else if (g.CanBeImmediate(index)) { // load [%base + #index]
- Emit(opcode | AddressingModeField::encode(kMode_MRI), output,
- g.UseRegister(base), g.UseImmediate(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MRI),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseImmediate(index));
} else { // load [%base + %index + K]
- Emit(opcode | AddressingModeField::encode(kMode_MR1I), output,
- g.UseRegister(base), g.UseRegister(index));
+ Emit(opcode | AddressingModeField::encode(kMode_MR1I),
+ g.DefineAsRegister(node), g.UseRegister(base),
g.UseRegister(index));
}
// TODO(turbofan): addressing modes [r+r*{2,4,8}+K]
}
@@ -128,16 +125,12 @@
}
DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
InstructionOperand* val;
- if (rep == kRepFloat32 || rep == kRepFloat64) {
- val = g.UseDoubleRegister(value);
+ if (g.CanBeImmediate(value)) {
+ val = g.UseImmediate(value);
+ } else if (rep == kRepWord8 || rep == kRepBit) {
+ val = g.UseByteRegister(value);
} else {
- if (g.CanBeImmediate(value)) {
- val = g.UseImmediate(value);
- } else if (rep == kRepWord8 || rep == kRepBit) {
- val = g.UseByteRegister(value);
- } else {
- val = g.UseRegister(value);
- }
+ val = g.UseRegister(value);
}
ArchOpcode opcode;
switch (rep) {
@@ -491,15 +484,14 @@
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
X64OperandGenerator g(this);
- Emit(kSSEInt32ToFloat64, g.DefineAsDoubleRegister(node),
- g.Use(node->InputAt(0)));
+ Emit(kSSEInt32ToFloat64, g.DefineAsRegister(node),
g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
X64OperandGenerator g(this);
// TODO(turbofan): X64 SSE cvtqsi2sd should support operands.
- Emit(kSSEUint32ToFloat64, g.DefineAsDoubleRegister(node),
+ Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
@@ -514,7 +506,7 @@
X64OperandGenerator g(this);
// TODO(turbofan): X64 SSE cvttsd2siq should support operands.
Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node),
- g.UseDoubleRegister(node->InputAt(0)));
+ g.UseRegister(node->InputAt(0)));
}
@@ -539,32 +531,28 @@
void InstructionSelector::VisitFloat64Add(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat64Add, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Sub(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Mul(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat64Mul, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitFloat64Div(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat64Div, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)));
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
@@ -572,8 +560,8 @@
X64OperandGenerator g(this);
InstructionOperand* temps[] = {g.TempRegister(rax)};
Emit(kSSEFloat64Mod, g.DefineSameAsFirst(node),
- g.UseDoubleRegister(node->InputAt(0)),
- g.UseDoubleRegister(node->InputAt(1)), 1, temps);
+ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), 1,
+ temps);
}
@@ -672,8 +660,7 @@
X64OperandGenerator g(this);
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
- VisitCompare(this, kSSEFloat64Cmp, g.UseDoubleRegister(left),
g.Use(right),
- cont);
+ VisitCompare(this, kSSEFloat64Cmp, g.UseRegister(left), g.Use(right),
cont);
}
--
--
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