Revision: 24047
Author: [email protected]
Date: Thu Sep 18 15:38:52 2014 UTC
Log: MIPS: Convert KeyedLoad indexed interceptor case to a Handler.
Port r24042 (eb9b9ec)
Original commit message:
Currently, KeyedLoads on objects with indexed interceptors are handled with
a
special stub. Instead, key on the map and handler mechanism for more uniform
treatment.
BUG=
[email protected]
Review URL: https://codereview.chromium.org/579273002
https://code.google.com/p/v8/source/detail?r=24047
Modified:
/branches/bleeding_edge/src/ic/mips64/ic-mips64.cc
/branches/bleeding_edge/src/mips64/code-stubs-mips64.cc
=======================================
--- /branches/bleeding_edge/src/ic/mips64/ic-mips64.cc Mon Sep 8 17:20:49
2014 UTC
+++ /branches/bleeding_edge/src/ic/mips64/ic-mips64.cc Thu Sep 18 15:38:52
2014 UTC
@@ -894,46 +894,6 @@
key, receiver, receiver_map,
elements_map,
elements);
}
-
-
-void KeyedLoadIC::GenerateIndexedInterceptor(MacroAssembler* masm) {
- // Return address is in ra.
- Label slow;
-
- Register receiver = LoadDescriptor::ReceiverRegister();
- Register key = LoadDescriptor::NameRegister();
- Register scratch1 = a3;
- Register scratch2 = a4;
- DCHECK(!scratch1.is(receiver) && !scratch1.is(key));
- DCHECK(!scratch2.is(receiver) && !scratch2.is(key));
-
- // Check that the receiver isn't a smi.
- __ JumpIfSmi(receiver, &slow);
-
- // Check that the key is an array index, that is Uint32.
- __ And(a4, key, Operand(kSmiTagMask | kSmiSignMask));
- __ Branch(&slow, ne, a4, Operand(zero_reg));
-
- // Get the map of the receiver.
- __ ld(scratch1, FieldMemOperand(receiver, HeapObject::kMapOffset));
-
- // Check that it has indexed interceptor and access checks
- // are not enabled for this object.
- __ lbu(scratch2, FieldMemOperand(scratch1, Map::kBitFieldOffset));
- __ And(scratch2, scratch2, Operand(kSlowCaseBitFieldMask));
- __ Branch(&slow, ne, scratch2, Operand(1 <<
Map::kHasIndexedInterceptor));
- // Everything is fine, call runtime.
- __ Push(receiver, key); // Receiver, key.
-
- // Perform tail call to the entry.
- __ TailCallExternalReference(
- ExternalReference(IC_Utility(kLoadElementWithInterceptor),
- masm->isolate()),
- 2, 1);
-
- __ bind(&slow);
- GenerateMiss(masm);
-}
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
=======================================
--- /branches/bleeding_edge/src/mips64/code-stubs-mips64.cc Thu Sep 18
15:36:42 2014 UTC
+++ /branches/bleeding_edge/src/mips64/code-stubs-mips64.cc Thu Sep 18
15:38:52 2014 UTC
@@ -1892,6 +1892,32 @@
__ sd(a2, MemOperand(sp, 0 * kPointerSize)); // Patch argument count.
__ TailCallRuntime(Runtime::kNewSloppyArguments, 3, 1);
}
+
+
+void LoadIndexedInterceptorStub::Generate(MacroAssembler* masm) {
+ // Return address is in ra.
+ Label slow;
+
+ Register receiver = LoadDescriptor::ReceiverRegister();
+ Register key = LoadDescriptor::NameRegister();
+
+ // Check that the key is an array index, that is Uint32.
+ __ And(t0, key, Operand(kSmiTagMask | kSmiSignMask));
+ __ Branch(&slow, ne, t0, Operand(zero_reg));
+
+ // Everything is fine, call runtime.
+ __ Push(receiver, key); // Receiver, key.
+
+ // Perform tail call to the entry.
+ __ TailCallExternalReference(
+ ExternalReference(IC_Utility(IC::kLoadElementWithInterceptor),
+ masm->isolate()),
+ 2, 1);
+
+ __ bind(&slow);
+ PropertyAccessCompiler::TailCallBuiltin(
+ masm, PropertyAccessCompiler::MissBuiltin(Code::KEYED_LOAD_IC));
+}
void ArgumentsAccessStub::GenerateNewStrict(MacroAssembler* masm) {
--
--
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