[v8-dev] [v8] r24092 committed - [turbofan] IA: Float64ToUint32 supports mem operand...

Fri, 19 Sep 2014 07:26:06 -0700 

Revision: 24092
Author:   [email protected]
Date:     Fri Sep 19 14:25:13 2014 UTC
Log:      [turbofan] IA: Float64ToUint32 supports mem operand

BUG=
[email protected]

Review URL: https://codereview.chromium.org/582713002

Patch from Weiliang Lin <[email protected]>.
https://code.google.com/p/v8/source/detail?r=24092

Modified:
 /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc
 /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
 /branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc
 /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
 /branches/bleeding_edge/src/ia32/assembler-ia32.cc
 /branches/bleeding_edge/src/ia32/assembler-ia32.h
 /branches/bleeding_edge/src/x64/assembler-x64.cc
 /branches/bleeding_edge/src/x64/assembler-x64.h
 /branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc
 /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc
 /branches/bleeding_edge/test/cctest/test-disasm-x64.cc

=======================================
--- /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Mon Sep 8 09:11:11 2014 UTC +++ /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -303,8 +303,7 @@
     case kSSEFloat64ToUint32: {
       XMMRegister scratch = xmm0;
       __ Move(scratch, -2147483648.0);
-      // TODO(turbofan): IA32 SSE subsd() should take an operand.
-      __ addsd(scratch, i.InputDoubleRegister(0));
+      __ addsd(scratch, i.InputOperand(0));
       __ cvttsd2si(i.OutputRegister(), scratch);
       __ add(i.OutputRegister(), Immediate(0x80000000));
       break;
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc Thu Sep 11 10:37:49 2014 UTC +++ /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -376,9 +376,7 @@

 void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
   IA32OperandGenerator g(this);
-  // TODO(turbofan): IA32 SSE subsd() should take an operand.
-  Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node),
-       g.UseRegister(node->InputAt(0)));
+ Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node), g.Use(node->InputAt(0))); 
 }


=======================================
--- /branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc Mon Sep 8 09:11:11 2014 UTC +++ /branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -469,8 +469,12 @@
       break;
     }
     case kSSEFloat64ToUint32: {
-      // TODO(turbofan): X64 SSE cvttsd2siq should support operands.
-      __ cvttsd2siq(i.OutputRegister(), i.InputDoubleRegister(0));
+      RegisterOrOperand input = i.InputRegisterOrOperand(0);
+      if (input.type == kDoubleRegister) {
+        __ cvttsd2siq(i.OutputRegister(), input.double_reg);
+      } else {
+        __ cvttsd2siq(i.OutputRegister(), input.operand);
+      }
__ andl(i.OutputRegister(), i.OutputRegister()); // clear upper bits. // TODO(turbofan): generated code should not look at the upper 32 bits 
       // of the result, but those bits could escape to the outside world.
=======================================
--- /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc Thu Sep 11 10:37:49 2014 UTC +++ /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -500,9 +500,7 @@

 void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
   X64OperandGenerator g(this);
-  // TODO(turbofan): X64 SSE cvttsd2siq should support operands.
-  Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node),
-       g.UseRegister(node->InputAt(0)));
+ Emit(kSSEFloat64ToUint32, g.DefineAsRegister(node), g.Use(node->InputAt(0))); 
 }


=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.cc Tue Sep 2 13:36:35 2014 UTC +++ /branches/bleeding_edge/src/ia32/assembler-ia32.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -2012,6 +2012,15 @@
   EMIT(0x5C);
   emit_sse_operand(dst, src);
 }
+
+
+void Assembler::subsd(XMMRegister dst, const Operand& src) {
+  EnsureSpace ensure_space(this);
+  EMIT(0xF2);
+  EMIT(0x0F);
+  EMIT(0x5C);
+  emit_sse_operand(dst, src);
+}


 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.h Wed Aug 6 13:56:58 2014 UTC +++ /branches/bleeding_edge/src/ia32/assembler-ia32.h Fri Sep 19 14:25:13 2014 UTC 
@@ -956,6 +956,7 @@
   void addsd(XMMRegister dst, XMMRegister src);
   void addsd(XMMRegister dst, const Operand& src);
   void subsd(XMMRegister dst, XMMRegister src);
+  void subsd(XMMRegister dst, const Operand& src);
   void mulsd(XMMRegister dst, XMMRegister src);
   void mulsd(XMMRegister dst, const Operand& src);
   void divsd(XMMRegister dst, XMMRegister src);
=======================================
--- /branches/bleeding_edge/src/x64/assembler-x64.cc Wed Sep 10 15:58:23 2014 UTC +++ /branches/bleeding_edge/src/x64/assembler-x64.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -2627,6 +2627,16 @@
   emit(0x2C);
   emit_sse_operand(dst, src);
 }
+
+
+void Assembler::cvttsd2siq(Register dst, const Operand& src) {
+  EnsureSpace ensure_space(this);
+  emit(0xF2);
+  emit_rex_64(dst, src);
+  emit(0x0F);
+  emit(0x2C);
+  emit_sse_operand(dst, src);
+}


 void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
@@ -2898,6 +2908,12 @@
   Register ireg = { reg.code() };
   emit_operand(ireg, adr);
 }
+
+
+void Assembler::emit_sse_operand(Register reg, const Operand& adr) {
+  Register ireg = {reg.code()};
+  emit_operand(ireg, adr);
+}


 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
=======================================
--- /branches/bleeding_edge/src/x64/assembler-x64.h Wed Aug 6 13:56:58 2014 UTC +++ /branches/bleeding_edge/src/x64/assembler-x64.h Fri Sep 19 14:25:13 2014 UTC 
@@ -1048,6 +1048,7 @@
   void cvttsd2si(Register dst, const Operand& src);
   void cvttsd2si(Register dst, XMMRegister src);
   void cvttsd2siq(Register dst, XMMRegister src);
+  void cvttsd2siq(Register dst, const Operand& src);

   void cvtlsi2sd(XMMRegister dst, const Operand& src);
   void cvtlsi2sd(XMMRegister dst, Register src);
@@ -1316,6 +1317,7 @@
// The first argument is the reg field, the second argument is the r/m field. 
   void emit_sse_operand(XMMRegister dst, XMMRegister src);
   void emit_sse_operand(XMMRegister reg, const Operand& adr);
+  void emit_sse_operand(Register reg, const Operand& adr);
   void emit_sse_operand(XMMRegister dst, Register src);
   void emit_sse_operand(Register dst, XMMRegister src);

=======================================
--- /branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc Wed Sep 10 12:23:45 2014 UTC +++ /branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -3230,6 +3230,46 @@
     CHECK_EQ(result[i], 100 + i);
   }
 }
+
+
+TEST(RunChangeFloat64ToUint32_spilled) {
+  RawMachineAssemblerTester<uint32_t> m;
+  const int kNumInputs = 32;
+  int32_t magic = 0x786234;
+  double input[kNumInputs];
+  uint32_t result[kNumInputs];
+  Node* input_node[kNumInputs];
+
+  for (int i = 0; i < kNumInputs; i++) {
+    input_node[i] =
+ m.Load(kMachFloat64, m.PointerConstant(&input), m.Int32Constant(i * 8)); 
+  }
+
+  for (int i = 0; i < kNumInputs; i++) {
+ m.Store(kMachUint32, m.PointerConstant(&result), m.Int32Constant(i * 4), 
+            m.ChangeFloat64ToUint32(input_node[i]));
+  }
+
+  m.Return(m.Int32Constant(magic));
+
+  for (int i = 0; i < kNumInputs; i++) {
+    if (i % 2) {
+      input[i] = 100 + i + 2147483648;
+    } else {
+      input[i] = 100 + i;
+    }
+  }
+
+  CHECK_EQ(magic, m.Call());
+
+  for (int i = 0; i < kNumInputs; i++) {
+    if (i % 2) {
+      CHECK_EQ(result[i], 100 + i + 2147483648);
+    } else {
+      CHECK_EQ(result[i], 100 + i);
+    }
+  }
+}


 TEST(RunDeadChangeFloat64ToInt32) {
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Fri Aug 22 11:43:39 2014 UTC +++ /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -416,6 +416,7 @@
     __ addsd(xmm1, xmm0);
     __ mulsd(xmm1, xmm0);
     __ subsd(xmm1, xmm0);
+    __ subsd(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ divsd(xmm1, xmm0);
     __ ucomisd(xmm0, xmm1);
     __ cmpltsd(xmm0, xmm1);
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-x64.cc Fri Aug 22 11:43:39 2014 UTC +++ /branches/bleeding_edge/test/cctest/test-disasm-x64.cc Fri Sep 19 14:25:13 2014 UTC 
@@ -378,6 +378,7 @@
     __ cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000));
     __ cvttsd2si(rdx, xmm1);
     __ cvttsd2siq(rdx, xmm1);
+    __ cvttsd2siq(rdx, Operand(rbx, rcx, times_4, 10000));
     __ movsd(xmm1, Operand(rbx, rcx, times_4, 10000));
     __ movsd(Operand(rbx, rcx, times_4, 10000), xmm1);
     // 128 bit move instructions.

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