Reviewers: danno, titzer, Benedikt Meurer,
Description:
[turbofan] IA: Uint32ToFloat64 supports mem operand.
BUG=
Please review this at https://codereview.chromium.org/583963002/
SVN Base: https://github.com/v8/v8.git@bleeding_edge
Affected files (+27, -15 lines):
M src/compiler/ia32/code-generator-ia32.cc
M src/compiler/ia32/instruction-selector-ia32.cc
M src/compiler/x64/code-generator-x64.cc
M src/compiler/x64/instruction-selector-x64.cc
M src/ia32/macro-assembler-ia32.h
M src/ia32/macro-assembler-ia32.cc
M src/x64/assembler-x64.cc
M test/cctest/test-disasm-x64.cc
Index: src/compiler/ia32/code-generator-ia32.cc
diff --git a/src/compiler/ia32/code-generator-ia32.cc
b/src/compiler/ia32/code-generator-ia32.cc
index
3a3fd795d8d38cd164fc68e7f6129265548d05f5..1e6a3c11749d35be1d74f1d2f01b3dd14cb9610d
100644
--- a/src/compiler/ia32/code-generator-ia32.cc
+++ b/src/compiler/ia32/code-generator-ia32.cc
@@ -313,8 +313,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ cvtsi2sd(i.OutputDoubleRegister(), i.InputOperand(0));
break;
case kSSEUint32ToFloat64:
- // TODO(turbofan): IA32 SSE LoadUint32() should take an operand.
- __ LoadUint32(i.OutputDoubleRegister(), i.InputRegister(0));
+ __ LoadUint32(i.OutputDoubleRegister(), i.InputOperand(0));
break;
case kIA32Movsxbl:
__ movsx_b(i.OutputRegister(), i.MemoryOperand());
Index: src/compiler/ia32/instruction-selector-ia32.cc
diff --git a/src/compiler/ia32/instruction-selector-ia32.cc
b/src/compiler/ia32/instruction-selector-ia32.cc
index
eb3752cde17046d30ceed70e224c2b9389940ed8..da99049f3fa7de6b3513ced2ca9ce047c2baeb7e
100644
--- a/src/compiler/ia32/instruction-selector-ia32.cc
+++ b/src/compiler/ia32/instruction-selector-ia32.cc
@@ -362,9 +362,7 @@ void
InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
IA32OperandGenerator g(this);
- // TODO(turbofan): IA32 SSE LoadUint32() should take an operand.
- Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
- g.UseRegister(node->InputAt(0)));
+ Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
g.Use(node->InputAt(0)));
}
Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc
b/src/compiler/x64/code-generator-x64.cc
index
f93ad21a219a09c0ca51f556dbf9d457a8a58ad1..c17da8f79b793f93d04ff0d3eebb3670d7afdb1d
100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -486,8 +486,12 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
}
case kSSEUint32ToFloat64: {
- // TODO(turbofan): X64 SSE cvtqsi2sd should support operands.
- __ cvtqsi2sd(i.OutputDoubleRegister(), i.InputRegister(0));
+ RegisterOrOperand input = i.InputRegisterOrOperand(0);
+ if (input.type == kRegister) {
+ __ cvtqsi2sd(i.OutputDoubleRegister(), input.reg);
+ } else {
+ __ cvtqsi2sd(i.OutputDoubleRegister(), input.operand);
+ }
break;
}
case kX64Movsxbl:
Index: src/compiler/x64/instruction-selector-x64.cc
diff --git a/src/compiler/x64/instruction-selector-x64.cc
b/src/compiler/x64/instruction-selector-x64.cc
index
8d41fa1871c906bc21b89ddb2b6762bae9d19f6e..2f8c491ba15c222154fb7743ac883331926a7beb
100644
--- a/src/compiler/x64/instruction-selector-x64.cc
+++ b/src/compiler/x64/instruction-selector-x64.cc
@@ -486,9 +486,7 @@ void
InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
X64OperandGenerator g(this);
- // TODO(turbofan): X64 SSE cvtqsi2sd should support operands.
- Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
- g.UseRegister(node->InputAt(0)));
+ Emit(kSSEUint32ToFloat64, g.DefineAsRegister(node),
g.Use(node->InputAt(0)));
}
Index: src/ia32/macro-assembler-ia32.cc
diff --git a/src/ia32/macro-assembler-ia32.cc
b/src/ia32/macro-assembler-ia32.cc
index
f938d500182161151c5ebf633dc6f5a8315790aa..d5aa0f834712eb52b1675f11b5a9f406ad1c37cd
100644
--- a/src/ia32/macro-assembler-ia32.cc
+++ b/src/ia32/macro-assembler-ia32.cc
@@ -346,12 +346,10 @@ void MacroAssembler::TruncateHeapNumberToI(Register
result_reg,
}
-void MacroAssembler::LoadUint32(XMMRegister dst,
- Register src) {
+void MacroAssembler::LoadUint32(XMMRegister dst, const Operand& src) {
Label done;
cmp(src, Immediate(0));
- ExternalReference uint32_bias =
- ExternalReference::address_of_uint32_bias();
+ ExternalReference uint32_bias =
ExternalReference::address_of_uint32_bias();
Cvtsi2sd(dst, src);
j(not_sign, &done, Label::kNear);
addsd(dst, Operand::StaticVariable(uint32_bias));
Index: src/ia32/macro-assembler-ia32.h
diff --git a/src/ia32/macro-assembler-ia32.h
b/src/ia32/macro-assembler-ia32.h
index
405bea8e73ff564cf11cd5e1eaa19fd82e33350b..5195e32d7ad8317b4a1208f5bb5aae9b422eb13c
100644
--- a/src/ia32/macro-assembler-ia32.h
+++ b/src/ia32/macro-assembler-ia32.h
@@ -484,7 +484,10 @@ class MacroAssembler: public Assembler {
j(not_carry, is_smi);
}
- void LoadUint32(XMMRegister dst, Register src);
+ void LoadUint32(XMMRegister dst, Register src) {
+ LoadUint32(dst, Operand(src));
+ }
+ void LoadUint32(XMMRegister dst, const Operand& src);
// Jump the register contains a smi.
inline void JumpIfSmi(Register value,
Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index
1dba9b031e59fad60c7542996d71b737cd3ccdbd..999563cece7429485ed54ae306eff53c4edfd872
100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -2659,6 +2659,16 @@ void Assembler::cvtlsi2ss(XMMRegister dst, Register
src) {
}
+void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_rex_64(dst, src);
+ emit(0x0F);
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
EnsureSpace ensure_space(this);
emit(0xF2);
Index: test/cctest/test-disasm-x64.cc
diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc
index
a842956ae82336fafa962bca1b8fe9e1935c1d1a..52de9da853b1b6fd27edd3fc5af165e084401abb
100644
--- a/test/cctest/test-disasm-x64.cc
+++ b/test/cctest/test-disasm-x64.cc
@@ -378,6 +378,8 @@ TEST(DisasmX64) {
__ cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000));
__ cvttsd2si(rdx, xmm1);
__ cvttsd2siq(rdx, xmm1);
+ __ cvtqsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000));
+ __ cvtqsi2sd(xmm1, rdx);
__ movsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ movsd(Operand(rbx, rcx, times_4, 10000), xmm1);
// 128 bit move instructions.
--
--
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