Reviewers: Benedikt Meurer, titzer, danno,
Message:
PTAL
Description:
[turbofan] x64: three operand imul supports first operand in memory location
BUG=
Please review this at https://codereview.chromium.org/596643003/
SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+18, -4 lines):
M src/compiler/x64/code-generator-x64.cc
M src/x64/assembler-x64.h
M src/x64/assembler-x64.cc
M test/cctest/test-disasm-x64.cc
Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc
b/src/compiler/x64/code-generator-x64.cc
index
0de838698bd75c081db0e3cb7dd26ee45a87882d..cdd35e276c8d956d166e14bafb0e91351a8fec7c
100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -275,8 +275,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (input.type == kRegister) {
__ imull(i.OutputRegister(), input.reg, i.InputImmediate(1));
} else {
- __ movq(kScratchRegister, input.operand);
- __ imull(i.OutputRegister(), kScratchRegister,
i.InputImmediate(1));
+ __ imull(i.OutputRegister(), input.operand, i.InputImmediate(1));
}
} else {
RegisterOrOperand input = i.InputRegisterOrOperand(1);
@@ -293,8 +292,7 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (input.type == kRegister) {
__ imulq(i.OutputRegister(), input.reg, i.InputImmediate(1));
} else {
- __ movq(kScratchRegister, input.operand);
- __ imulq(i.OutputRegister(), kScratchRegister,
i.InputImmediate(1));
+ __ imulq(i.OutputRegister(), input.operand, i.InputImmediate(1));
}
} else {
RegisterOrOperand input = i.InputRegisterOrOperand(1);
Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index
4f8d5b1be13e443e77e2fbba613b550eaa314acb..ce68524524cc331953bf649eedf48b829931a5af
100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -942,6 +942,20 @@ void Assembler::emit_imul(Register dst, Register src,
Immediate imm, int size) {
}
+void Assembler::emit_imul(Register dst, const Operand& src, Immediate imm,
+ int size) {
+ EnsureSpace ensure_space(this);
+ emit_rex(dst, src, size);
+ if (is_int8(imm.value_)) {
+ emit(0x6B);
+ } else {
+ emit(0x69);
+ }
+ emit_operand(dst, src);
+ emit(imm.value_);
+}
+
+
void Assembler::emit_inc(Register dst, int size) {
EnsureSpace ensure_space(this);
emit_rex(dst, size);
Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index
b2a97cc64208572b297a65ea73a07f52dc61f0f9..9363c07536a42e03c6dbd70c9b2cc178955fe004
100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -1449,6 +1449,7 @@ class Assembler : public AssemblerBase {
void emit_imul(Register dst, Register src, int size);
void emit_imul(Register dst, const Operand& src, int size);
void emit_imul(Register dst, Register src, Immediate imm, int size);
+ void emit_imul(Register dst, const Operand& src, Immediate imm, int
size);
void emit_inc(Register dst, int size);
void emit_inc(const Operand& dst, int size);
Index: test/cctest/test-disasm-x64.cc
diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc
index
e756ce220b6817cbb65e61554c8f325e9d6961d3..d238410fa4b30cbde089d5952a49c37bef5d04e9
100644
--- a/test/cctest/test-disasm-x64.cc
+++ b/test/cctest/test-disasm-x64.cc
@@ -167,6 +167,7 @@ TEST(DisasmX64) {
__ imulq(rdx, Operand(rbx, rcx, times_4, 10000));
__ imulq(rdx, rcx, Immediate(12));
__ imulq(rdx, rcx, Immediate(1000));
+ __ imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(1000));
__ incq(rdx);
__ incq(Operand(rbx, rcx, times_4, 10000));
--
--
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