Revision: 24387
Author: [email protected]
Date: Thu Oct 2 09:04:04 2014 UTC
Log: [turbofan] support all shift operands on ia32
[email protected]
BUG=
Review URL: https://codereview.chromium.org/619663002
https://code.google.com/p/v8/source/detail?r=24387
Modified:
/branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc
/branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
/branches/bleeding_edge/src/ia32/assembler-ia32.cc
/branches/bleeding_edge/src/ia32/assembler-ia32.h
/branches/bleeding_edge/test/cctest/test-disasm-ia32.cc
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Wed
Oct 1 14:03:02 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Thu
Oct 2 09:04:04 2014 UTC
@@ -32,8 +32,6 @@
}
Operand OutputOperand() { return ToOperand(instr_->Output()); }
-
- Operand TempOperand(int index) { return
ToOperand(instr_->TempAt(index)); }
Operand ToOperand(InstructionOperand* op, int extra = 0) {
if (op->IsRegister()) {
@@ -283,30 +281,30 @@
break;
case kIA32Shl:
if (HasImmediateInput(instr, 1)) {
- __ shl(i.OutputRegister(), i.InputInt5(1));
+ __ shl(i.OutputOperand(), i.InputInt5(1));
} else {
- __ shl_cl(i.OutputRegister());
+ __ shl_cl(i.OutputOperand());
}
break;
case kIA32Shr:
if (HasImmediateInput(instr, 1)) {
- __ shr(i.OutputRegister(), i.InputInt5(1));
+ __ shr(i.OutputOperand(), i.InputInt5(1));
} else {
- __ shr_cl(i.OutputRegister());
+ __ shr_cl(i.OutputOperand());
}
break;
case kIA32Sar:
if (HasImmediateInput(instr, 1)) {
- __ sar(i.OutputRegister(), i.InputInt5(1));
+ __ sar(i.OutputOperand(), i.InputInt5(1));
} else {
- __ sar_cl(i.OutputRegister());
+ __ sar_cl(i.OutputOperand());
}
break;
case kIA32Ror:
if (HasImmediateInput(instr, 1)) {
- __ ror(i.OutputRegister(), i.InputInt5(1));
+ __ ror(i.OutputOperand(), i.InputInt5(1));
} else {
- __ ror_cl(i.OutputRegister());
+ __ ror_cl(i.OutputOperand());
}
break;
case kSSEFloat64Cmp:
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Wed Oct 1 10:47:14 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Thu Oct 2 09:04:04 2014 UTC
@@ -329,9 +329,8 @@
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
- // TODO(turbofan): assembler only supports some addressing modes for
shifts.
if (g.CanBeImmediate(right)) {
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseImmediate(right));
} else {
Int32BinopMatcher m(node);
@@ -341,7 +340,7 @@
right = mright.left().node();
}
}
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseFixed(right, ecx));
}
}
=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.cc Thu Sep 25 08:33:24
2014 UTC
+++ /branches/bleeding_edge/src/ia32/assembler-ia32.cc Thu Oct 2 09:04:04
2014 UTC
@@ -982,24 +982,24 @@
}
-void Assembler::ror(Register dst, uint8_t imm8) {
+void Assembler::ror(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
} else {
EMIT(0xC1);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
EMIT(imm8);
}
}
-void Assembler::ror_cl(Register dst) {
+void Assembler::ror_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
- EMIT(0xC8 | dst.code());
+ emit_operand(ecx, dst);
}
=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.h Thu Sep 25 08:33:24
2014 UTC
+++ /branches/bleeding_edge/src/ia32/assembler-ia32.h Thu Oct 2 09:04:04
2014 UTC
@@ -740,8 +740,11 @@
void rcl(Register dst, uint8_t imm8);
void rcr(Register dst, uint8_t imm8);
- void ror(Register dst, uint8_t imm8);
- void ror_cl(Register dst);
+
+ void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
+ void ror(const Operand& dst, uint8_t imm8);
+ void ror_cl(Register dst) { ror_cl(Operand(dst)); }
+ void ror_cl(const Operand& dst);
void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
void sar(const Operand& dst, uint8_t imm8);
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Fri Sep 19
14:25:13 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Thu Oct 2
09:04:04 2014 UTC
@@ -201,6 +201,12 @@
__ rcl(edx, 7);
__ rcr(edx, 1);
__ rcr(edx, 7);
+ __ ror(edx, 1);
+ __ ror(edx, 6);
+ __ ror_cl(edx);
+ __ ror(Operand(ebx, ecx, times_4, 10000), 1);
+ __ ror(Operand(ebx, ecx, times_4, 10000), 6);
+ __ ror_cl(Operand(ebx, ecx, times_4, 10000));
__ sar(edx, 1);
__ sar(edx, 6);
__ sar_cl(edx);
--
--
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