Reviewers: danno, Jakob, paul.l..., akos.palfi.imgtec, balazs.kilvady, gergely.kis.imgtec,

Message:
PTAL.

Description:
MIPS: Improve runtime detection and compatibility wrt arch. revisions.

TEST=
BUG=

Please review this at https://codereview.chromium.org/618193005/

SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge

Affected files (+55, -20 lines):
  M build/toolchain.gypi
  M src/base/cpu.cc
  M src/mips/constants-mips.h


Index: build/toolchain.gypi
diff --git a/build/toolchain.gypi b/build/toolchain.gypi
index b04f661d8571623cb634df3a5a7736ed0fa804ec..a7410754598e3a70299e10e11875c8315beb7a75 100644
--- a/build/toolchain.gypi
+++ b/build/toolchain.gypi
@@ -302,7 +302,7 @@
                     'cflags': ['-mfp32'],
                   }],
                   ['mips_arch_variant=="r6"', {
-                    'cflags!': ['-mfp32'],
+                    'cflags!': ['-mfp32', '-mfpxx'],
                     'cflags': ['-mips32r6', '-Wa,-mips32r6'],
                     'ldflags': [
                       '-mips32r6',
@@ -312,14 +312,17 @@
                   }],
                   ['mips_arch_variant=="r2"', {
                     'cflags': ['-mips32r2', '-Wa,-mips32r2'],
+                    'ldflags': ['-mips32r2'],
                   }],
                   ['mips_arch_variant=="r1"', {
-                    'cflags!': ['-mfp64'],
+                    'cflags!': ['-mfp64', '-mfpxx'],
                     'cflags': ['-mips32', '-Wa,-mips32'],
+                    'ldflags': ['-mips32'],
                   }],
                   ['mips_arch_variant=="rx"', {
-                    'cflags!': ['-mfp64'],
-                    'cflags': ['-mips32', '-Wa,-mips32'],
+                    'cflags!': ['-mfp64', '-mfp32'],
+                    'cflags': ['-mips32', '-Wa,-mips32', '-mfpxx'],
+                    'ldflags': ['-mips32'],
                   }],
                 ],
               }],
@@ -400,7 +403,7 @@
                     'cflags': ['-mfp32'],
                   }],
                   ['mips_arch_variant=="r6"', {
-                    'cflags!': ['-mfp32'],
+                    'cflags!': ['-mfp32', '-mfpxx'],
                     'cflags': ['-mips32r6', '-Wa,-mips32r6'],
                     'ldflags': [
                       '-mips32r6',
@@ -410,17 +413,20 @@
                   }],
                   ['mips_arch_variant=="r2"', {
                     'cflags': ['-mips32r2', '-Wa,-mips32r2'],
+                    'ldflags': ['-mips32r2'],
                   }],
                   ['mips_arch_variant=="r1"', {
-                    'cflags!': ['-mfp64'],
+                    'cflags!': ['-mfp64', '-mfpxx'],
                     'cflags': ['-mips32', '-Wa,-mips32'],
+                    'ldflags': ['-mips32'],
                   }],
                   ['mips_arch_variant=="rx"', {
-                    'cflags!': ['-mfp64'],
-                    'cflags': ['-mips32', '-Wa,-mips32'],
+                    'cflags!': ['-mfp64', '-mfp32'],
+                    'cflags': ['-mips32', '-Wa,-mips32', '-mfpxx'],
+                    'ldflags': ['-mips32'],
                   }],
                   ['mips_arch_variant=="loongson"', {
-                    'cflags!': ['-mfp64'],
+                    'cflags!': ['-mfp64', '-mfp32', '-mfpxx'],
                     'cflags': ['-mips3', '-Wa,-mips3'],
                   }],
                 ],
Index: src/base/cpu.cc
diff --git a/src/base/cpu.cc b/src/base/cpu.cc
index fbfbcf683b74e3014257cfe749e96eabdf2203cf..0a737a66d488e090e611f40440f64e001708123b 100644
--- a/src/base/cpu.cc
+++ b/src/base/cpu.cc
@@ -119,13 +119,18 @@ static uint32_t ReadELFHWCaps() {
 int __detect_fp64_mode(void) {
   double result = 0;
   // Bit representation of (double)1 is 0x3FF0000000000000.
-  asm(
-    "lui $t0, 0x3FF0\n\t"
-    "ldc1 $f0, %0\n\t"
-    "mtc1 $t0, $f1\n\t"
-    "sdc1 $f0, %0\n\t"
-    : "+m" (result)
-    : : "t0", "$f0", "$f1", "memory");
+  __asm__ volatile(
+      ".set push\n\t"
+      ".set noreorder\n\t"
+      ".set oddspreg\n\t"
+      "lui $t0, 0x3FF0\n\t"
+      "ldc1 $f0, %0\n\t"
+      "mtc1 $t0, $f1\n\t"
+      "sdc1 $f0, %0\n\t"
+      ".set pop\n\t"
+      : "+m"(result)
+      :
+      : "t0", "$f0", "$f1", "memory");

   return !(result == 1);
 }
@@ -133,9 +138,33 @@ int __detect_fp64_mode(void) {

 int __detect_mips_arch_revision(void) {
// TODO(dusmil): Do the specific syscall as soon as it is implemented in mips
-  // kernel. Currently fail-back to the least common denominator which is
-  // mips32 revision 1.
-  return 1;
+  // kernel.
+  // Detect r6 architectures through QNaN representation.
+ // The r6 variant uses IEEE2008 QNaN representation which is 7ff8xxxxxxxxxxxx,
+  // the same encoding for QNaN on x86, ARM.
+ // Non r6 variants uses 7ff7fxxxxxxxxxxx for QNaN which is SNaN on x86, ARM.
+  double result = 0;
+  uint64_t check, mask = 0x8000000000000LLU;
+  union {
+    double d;
+    uint64_t ull;
+  } conv;
+
+  __asm__ volatile(
+      ".set push\n\t"
+      ".set noreorder\n\t"
+      "ldc1 $f0, %0\n\t"
+      "div.d $f0, $f0, $f0\n\t"
+      "sdc1 $f0, %0\n\t"
+      ".set pop\n\t"
+      : "+m"(result)
+      :
+      : "$f0", "memory");
+  conv.d = result;
+  // Check bit 50 of NaN value.
+  // Fail-back to the least common denominator which is mips32 revision 1.
+  check = conv.ull & mask;
+  return check ? 6 : 1;
 }
 #endif

Index: src/mips/constants-mips.h
diff --git a/src/mips/constants-mips.h b/src/mips/constants-mips.h
index 5ead1105ee7366831359ab54aa696d54f6bcc352..c2eb4cae1ecb477162dadb3fd037dd4d147d7183 100644
--- a/src/mips/constants-mips.h
+++ b/src/mips/constants-mips.h
@@ -105,7 +105,7 @@ const uint32_t kHoleNanLower32Offset = 4;
   (kArchVariant == check)
 #else
 #define IsMipsArchVariant(check) \
-  (CpuFeatures::IsSupported(check))
+  (CpuFeatures::IsSupported(static_cast<CpuFeature>(check)))
 #endif




--
--
v8-dev mailing list
[email protected]
http://groups.google.com/group/v8-dev
--- You received this message because you are subscribed to the Google Groups "v8-dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to [email protected].
For more options, visit https://groups.google.com/d/optout.

Reply via email to