[v8-dev] [turbofan]IA: ChangeFloat32ToFloat64 supports mem operand (issue 641153003 by [email protected])

Fri, 10 Oct 2014 00:34:32 -0700 

Reviewers: Benedikt Meurer, titzer, dcarney, danno,

Description:
[turbofan]IA: ChangeFloat32ToFloat64 supports mem operand

BUG=

Please review this at https://codereview.chromium.org/641153003/

SVN Base: https://github.com/v8/v8.git@bleeding_edge

Affected files (+47, -8 lines):
  M src/compiler/ia32/code-generator-ia32.cc
  M src/compiler/ia32/instruction-selector-ia32.cc
  M src/compiler/x64/code-generator-x64.cc
  M src/compiler/x64/instruction-selector-x64.cc
  M src/ia32/assembler-ia32.h
  M src/ia32/assembler-ia32.cc
  M test/cctest/compiler/test-run-machops.cc
  M test/cctest/test-disasm-ia32.cc


Index: src/compiler/ia32/code-generator-ia32.cc
diff --git a/src/compiler/ia32/code-generator-ia32.cc b/src/compiler/ia32/code-generator-ia32.cc index 0c71bf3de2e44e5d49258950931d3504d6fa83d3..5a6dbc688a2f61fb845232d20878f6c0052dbfaa 100644 
--- a/src/compiler/ia32/code-generator-ia32.cc
+++ b/src/compiler/ia32/code-generator-ia32.cc
@@ -351,7 +351,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { 
       __ sqrtsd(i.OutputDoubleRegister(), i.InputOperand(0));
       break;
     case kSSECvtss2sd:
-      __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+      __ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
       break;
     case kSSECvtsd2ss:
       __ cvtsd2ss(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
Index: src/compiler/ia32/instruction-selector-ia32.cc
diff --git a/src/compiler/ia32/instruction-selector-ia32.cc b/src/compiler/ia32/instruction-selector-ia32.cc index dee53c9559fc97c0188f20f41e087963a00e3640..54b40847df282a6735632c227c269fca76fe6528 100644 
--- a/src/compiler/ia32/instruction-selector-ia32.cc
+++ b/src/compiler/ia32/instruction-selector-ia32.cc
@@ -499,8 +499,7 @@ void InstructionSelector::VisitUint32Mod(Node* node) {

 void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
   IA32OperandGenerator g(this);
-  // TODO(turbofan): IA32 SSE conversions should take an operand.
- Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); 
+  Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }


Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc index de8956e01d248a1ce47b76b297fae2aee4e5080f..45b0cdc0df6aaa64fb790382df680de8f7d4f56c 100644 
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -405,7 +405,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { 
       }
       break;
     case kSSECvtss2sd:
-      __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+      if (instr->InputAt(0)->IsDoubleRegister()) {
+        __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+      } else {
+        __ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
+      }
       break;
     case kSSECvtsd2ss:
       __ cvtsd2ss(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
Index: src/compiler/x64/instruction-selector-x64.cc
diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc index 7f9e40afe2c4a2209b929b7d71440968b84576e1..d3fd8f2d742bea2200413a7e9ff05b7bab1984f4 100644 
--- a/src/compiler/x64/instruction-selector-x64.cc
+++ b/src/compiler/x64/instruction-selector-x64.cc
@@ -608,8 +608,7 @@ void InstructionSelector::VisitUint64Mod(Node* node) {

 void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
   X64OperandGenerator g(this);
-  // TODO(turbofan): X64 SSE conversions should take an operand.
- Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); 
+  Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }


Index: src/ia32/assembler-ia32.cc
diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc
index 7a9b963488b7909f0143dd06003d2d0eafc52b1d..c79a5a2ae01a5c715dc95187e02019186d1c2a5f 100644 
--- a/src/ia32/assembler-ia32.cc
+++ b/src/ia32/assembler-ia32.cc
@@ -1951,7 +1951,7 @@ void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) { 
 }


-void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
+void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0xF3);
   EMIT(0x0F);
Index: src/ia32/assembler-ia32.h
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h
index 3cab0e444df0345a248a3655b498c9d08ce1ef94..8c1dcecdfd38cff6fe789cccc217e3173388caf4 100644 
--- a/src/ia32/assembler-ia32.h
+++ b/src/ia32/assembler-ia32.h
@@ -958,7 +958,10 @@ class Assembler : public AssemblerBase {
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); } 
   void cvtsi2sd(XMMRegister dst, const Operand& src);
-  void cvtss2sd(XMMRegister dst, XMMRegister src);
+  void cvtss2sd(XMMRegister dst, const Operand& src);
+  void cvtss2sd(XMMRegister dst, XMMRegister src) {
+    cvtss2sd(dst, Operand(src));
+  }
   void cvtsd2ss(XMMRegister dst, XMMRegister src);

   void addsd(XMMRegister dst, XMMRegister src);
Index: test/cctest/compiler/test-run-machops.cc
diff --git a/test/cctest/compiler/test-run-machops.cc b/test/cctest/compiler/test-run-machops.cc index 55a8ae7d4ac053f36ca4471529abe365fb6895ad..f3d08588f52452884e18d890b9efba7901f2239c 100644 
--- a/test/cctest/compiler/test-run-machops.cc
+++ b/test/cctest/compiler/test-run-machops.cc
@@ -4307,6 +4307,38 @@ TEST(RunChangeFloat32ToFloat64) {
 }


+TEST(RunChangeFloat32ToFloat64_spilled) {
+  RawMachineAssemblerTester<int32_t> m;
+  const int kNumInputs = 32;
+  int32_t magic = 0x786234;
+  float input[kNumInputs];
+  double result[kNumInputs];
+  Node* input_node[kNumInputs];
+
+  for (int i = 0; i < kNumInputs; i++) {
+    input_node[i] =
+ m.Load(kMachFloat32, m.PointerConstant(&input), m.Int32Constant(i * 4)); 
+  }
+
+  for (int i = 0; i < kNumInputs; i++) {
+ m.Store(kMachFloat64, m.PointerConstant(&result), m.Int32Constant(i * 8), 
+            m.ChangeFloat32ToFloat64(input_node[i]));
+  }
+
+  m.Return(m.Int32Constant(magic));
+
+  for (int i = 0; i < kNumInputs; i++) {
+    input[i] = 100.9f + i;
+  }
+
+  CHECK_EQ(magic, m.Call());
+
+  for (int i = 0; i < kNumInputs; i++) {
+    CHECK_EQ(result[i], static_cast<double>(input[i]));
+  }
+}
+
+
 TEST(RunTruncateFloat64ToFloat32) {
   float actual = 0.0f;
   double input = 0.0;
Index: test/cctest/test-disasm-ia32.cc
diff --git a/test/cctest/test-disasm-ia32.cc b/test/cctest/test-disasm-ia32.cc index 8615d86086b964ff5368ec43fd2c0af7934457f9..6eee3023e8abbd6908e3190878928372f9d7f9ba 100644 
--- a/test/cctest/test-disasm-ia32.cc
+++ b/test/cctest/test-disasm-ia32.cc
@@ -411,6 +411,8 @@ TEST(DisasmIa320) {
   {
     __ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000));
     __ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
+    __ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
+    __ cvtss2sd(xmm1, xmm0);
     __ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
     __ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
     // 128 bit move instructions.


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