Revision: 24542
Author: [email protected]
Date: Mon Oct 13 07:42:35 2014 UTC
Log: [turbofan]IA: ChangeFloat32ToFloat64 supports mem operand
BUG=
[email protected]
Review URL: https://codereview.chromium.org/641153003
Patch from Jing Bao <[email protected]>.
https://code.google.com/p/v8/source/detail?r=24542
Modified:
/branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc
/branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
/branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc
/branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
/branches/bleeding_edge/src/ia32/assembler-ia32.cc
/branches/bleeding_edge/src/ia32/assembler-ia32.h
/branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc
/branches/bleeding_edge/test/cctest/test-disasm-ia32.cc
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Mon
Oct 13 07:12:57 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/code-generator-ia32.cc Mon
Oct 13 07:42:35 2014 UTC
@@ -351,7 +351,7 @@
__ sqrtsd(i.OutputDoubleRegister(), i.InputOperand(0));
break;
case kSSECvtss2sd:
- __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+ __ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
break;
case kSSECvtsd2ss:
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0));
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Mon Oct 13 07:12:57 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Mon Oct 13 07:42:35 2014 UTC
@@ -499,8 +499,7 @@
void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
IA32OperandGenerator g(this);
- // TODO(turbofan): IA32 SSE conversions should take an operand.
- Emit(kSSECvtss2sd, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
+ Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
=======================================
--- /branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc Mon Oct
13 07:12:57 2014 UTC
+++ /branches/bleeding_edge/src/compiler/x64/code-generator-x64.cc Mon Oct
13 07:42:35 2014 UTC
@@ -405,7 +405,11 @@
}
break;
case kSSECvtss2sd:
- __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+ if (instr->InputAt(0)->IsDoubleRegister()) {
+ __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
+ } else {
+ __ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
+ }
break;
case kSSECvtsd2ss:
if (instr->InputAt(0)->IsDoubleRegister()) {
=======================================
--- /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Mon Oct 13 07:12:57 2014 UTC
+++ /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Mon Oct 13 07:42:35 2014 UTC
@@ -608,8 +608,7 @@
void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
X64OperandGenerator g(this);
- // TODO(turbofan): X64 SSE conversions should take an operand.
- Emit(kSSECvtss2sd, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
+ Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.cc Mon Oct 13 07:12:57
2014 UTC
+++ /branches/bleeding_edge/src/ia32/assembler-ia32.cc Mon Oct 13 07:42:35
2014 UTC
@@ -1951,7 +1951,7 @@
}
-void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
+void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
=======================================
--- /branches/bleeding_edge/src/ia32/assembler-ia32.h Mon Oct 13 07:12:57
2014 UTC
+++ /branches/bleeding_edge/src/ia32/assembler-ia32.h Mon Oct 13 07:42:35
2014 UTC
@@ -958,12 +958,14 @@
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst,
Operand(src)); }
void cvtsi2sd(XMMRegister dst, const Operand& src);
- void cvtss2sd(XMMRegister dst, XMMRegister src);
+ void cvtss2sd(XMMRegister dst, const Operand& src);
+ void cvtss2sd(XMMRegister dst, XMMRegister src) {
+ cvtss2sd(dst, Operand(src));
+ }
void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, XMMRegister src) {
cvtsd2ss(dst, Operand(src));
}
-
void addsd(XMMRegister dst, XMMRegister src);
void addsd(XMMRegister dst, const Operand& src);
void subsd(XMMRegister dst, XMMRegister src);
=======================================
--- /branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc Mon
Oct 13 07:12:57 2014 UTC
+++ /branches/bleeding_edge/test/cctest/compiler/test-run-machops.cc Mon
Oct 13 07:42:35 2014 UTC
@@ -4337,6 +4337,38 @@
CHECK_EQ(expected, actual);
}
}
+
+
+TEST(RunChangeFloat32ToFloat64_spilled) {
+ RawMachineAssemblerTester<int32_t> m;
+ const int kNumInputs = 32;
+ int32_t magic = 0x786234;
+ float input[kNumInputs];
+ double result[kNumInputs];
+ Node* input_node[kNumInputs];
+
+ for (int i = 0; i < kNumInputs; i++) {
+ input_node[i] =
+ m.Load(kMachFloat32, m.PointerConstant(&input), m.Int32Constant(i
* 4));
+ }
+
+ for (int i = 0; i < kNumInputs; i++) {
+ m.Store(kMachFloat64, m.PointerConstant(&result), m.Int32Constant(i *
8),
+ m.ChangeFloat32ToFloat64(input_node[i]));
+ }
+
+ m.Return(m.Int32Constant(magic));
+
+ for (int i = 0; i < kNumInputs; i++) {
+ input[i] = 100.9f + i;
+ }
+
+ CHECK_EQ(magic, m.Call());
+
+ for (int i = 0; i < kNumInputs; i++) {
+ CHECK_EQ(result[i], static_cast<double>(input[i]));
+ }
+}
TEST(RunTruncateFloat64ToFloat32) {
=======================================
--- /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Mon Oct 13
07:12:57 2014 UTC
+++ /branches/bleeding_edge/test/cctest/test-disasm-ia32.cc Mon Oct 13
07:42:35 2014 UTC
@@ -413,6 +413,8 @@
{
__ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000));
__ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
+ __ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
+ __ cvtss2sd(xmm1, xmm0);
__ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
// 128 bit move instructions.
--
--
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