Revision: 24580
Author: [email protected]
Date: Tue Oct 14 08:34:20 2014 UTC
Log: [turbofan] Use register for instruction operands when SameAsFirst
is specified.
As the register allocator cannot reuse spill slots, SameAsFirst
constraint means that we would have to do an expensive move to a
differen spill slot if we choose to spill. Forcing the operand
to a register is cheaper.
In zlib, we get >10% speed-up for ia32, >25% for x64.
BUG=
[email protected]
Review URL: https://codereview.chromium.org/650083003
https://code.google.com/p/v8/source/detail?r=24580
Modified:
/branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
/branches/bleeding_edge/src/compiler/instruction-selector-impl.h
/branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
=======================================
--- /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Mon Oct 13 08:15:03 2014 UTC
+++ /branches/bleeding_edge/src/compiler/ia32/instruction-selector-ia32.cc
Tue Oct 14 08:34:20 2014 UTC
@@ -260,7 +260,7 @@
// TODO(turbofan): match complex addressing modes.
if (g.CanBeImmediate(right)) {
- inputs[input_count++] = g.Use(left);
+ inputs[input_count++] = g.UseRegister(left);
inputs[input_count++] = g.UseImmediate(right);
} else {
if (node->op()->HasProperty(Operator::kCommutative) &&
@@ -315,7 +315,7 @@
IA32OperandGenerator g(this);
Int32BinopMatcher m(node);
if (m.right().Is(-1)) {
- Emit(kIA32Not, g.DefineSameAsFirst(node), g.Use(m.left().node()));
+ Emit(kIA32Not, g.DefineSameAsFirst(node),
g.UseRegister(m.left().node()));
} else {
VisitBinop(this, node, kIA32Xor);
}
@@ -330,7 +330,7 @@
Node* right = node->InputAt(1);
if (g.CanBeImmediate(right)) {
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseImmediate(right));
} else {
Int32BinopMatcher m(node);
@@ -340,7 +340,7 @@
right = mright.left().node();
}
}
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseFixed(right, ecx));
}
}
=======================================
--- /branches/bleeding_edge/src/compiler/instruction-selector-impl.h Mon
Oct 13 08:09:27 2014 UTC
+++ /branches/bleeding_edge/src/compiler/instruction-selector-impl.h Tue
Oct 14 08:34:20 2014 UTC
@@ -55,9 +55,9 @@
}
InstructionOperand* Use(Node* node) {
- return Use(node,
- new (zone()) UnallocatedOperand(
- UnallocatedOperand::ANY,
UnallocatedOperand::USED_AT_START));
+ return Use(
+ node, new (zone()) UnallocatedOperand(
+ UnallocatedOperand::NONE,
UnallocatedOperand::USED_AT_START));
}
InstructionOperand* UseRegister(Node* node) {
@@ -69,7 +69,7 @@
// Use register or operand for the node. If a register is chosen, it
won't
// alias any temporary or output registers.
InstructionOperand* UseUnique(Node* node) {
- return Use(node, new (zone())
UnallocatedOperand(UnallocatedOperand::ANY));
+ return Use(node, new (zone())
UnallocatedOperand(UnallocatedOperand::NONE));
}
// Use a unique register for the node that does not alias any temporary
or
=======================================
--- /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Mon Oct 13 08:15:03 2014 UTC
+++ /branches/bleeding_edge/src/compiler/x64/instruction-selector-x64.cc
Tue Oct 14 08:34:20 2014 UTC
@@ -241,7 +241,7 @@
// TODO(turbofan): match complex addressing modes.
if (g.CanBeImmediate(right)) {
- inputs[input_count++] = g.Use(left);
+ inputs[input_count++] = g.UseRegister(left);
inputs[input_count++] = g.UseImmediate(right);
} else {
if (node->op()->HasProperty(Operator::kCommutative) &&
@@ -305,7 +305,7 @@
X64OperandGenerator g(this);
Uint32BinopMatcher m(node);
if (m.right().Is(-1)) {
- Emit(kX64Not32, g.DefineSameAsFirst(node), g.Use(m.left().node()));
+ Emit(kX64Not32, g.DefineSameAsFirst(node),
g.UseRegister(m.left().node()));
} else {
VisitBinop(this, node, kX64Xor32);
}
@@ -316,7 +316,7 @@
X64OperandGenerator g(this);
Uint64BinopMatcher m(node);
if (m.right().Is(-1)) {
- Emit(kX64Not, g.DefineSameAsFirst(node), g.Use(m.left().node()));
+ Emit(kX64Not, g.DefineSameAsFirst(node),
g.UseRegister(m.left().node()));
} else {
VisitBinop(this, node, kX64Xor);
}
@@ -332,7 +332,7 @@
Node* right = node->InputAt(1);
if (g.CanBeImmediate(right)) {
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseImmediate(right));
} else {
Int32BinopMatcher m(node);
@@ -342,7 +342,7 @@
right = mright.left().node();
}
}
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseFixed(right, rcx));
}
}
@@ -357,7 +357,7 @@
Node* right = node->InputAt(1);
if (g.CanBeImmediate(right)) {
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseImmediate(right));
} else {
Int64BinopMatcher m(node);
@@ -367,7 +367,7 @@
right = mright.left().node();
}
}
- selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
+ selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
g.UseFixed(right, rcx));
}
}
@@ -472,7 +472,7 @@
X64OperandGenerator g(this);
Int32BinopMatcher m(node);
if (m.left().Is(0)) {
- Emit(kX64Neg32, g.DefineSameAsFirst(node), g.Use(m.right().node()));
+ Emit(kX64Neg32, g.DefineSameAsFirst(node),
g.UseRegister(m.right().node()));
} else {
VisitBinop(this, node, kX64Sub32);
}
@@ -483,7 +483,7 @@
X64OperandGenerator g(this);
Int64BinopMatcher m(node);
if (m.left().Is(0)) {
- Emit(kX64Neg, g.DefineSameAsFirst(node), g.Use(m.right().node()));
+ Emit(kX64Neg, g.DefineSameAsFirst(node),
g.UseRegister(m.right().node()));
} else {
VisitBinop(this, node, kX64Sub);
}
--
--
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