Revision: 25081
Author: [email protected]
Date: Mon Nov 3 16:40:54 2014 UTC
Log: MIPS: [turbofan] Also optimize unsigned division by constant.
Port r25061 (7fe697f)
TEST=cctest,mjsunit,unittests
BUG=
[email protected]
Review URL: https://codereview.chromium.org/701543002
https://code.google.com/p/v8/source/detail?r=25081
Modified:
/branches/bleeding_edge/src/compiler/mips/code-generator-mips.cc
/branches/bleeding_edge/src/compiler/mips/instruction-codes-mips.h
/branches/bleeding_edge/src/compiler/mips/instruction-selector-mips.cc
/branches/bleeding_edge/src/mips/macro-assembler-mips.cc
/branches/bleeding_edge/src/mips/macro-assembler-mips.h
=======================================
--- /branches/bleeding_edge/src/compiler/mips/code-generator-mips.cc Mon
Oct 27 12:39:20 2014 UTC
+++ /branches/bleeding_edge/src/compiler/mips/code-generator-mips.cc Mon
Nov 3 16:40:54 2014 UTC
@@ -188,6 +188,9 @@
case kMipsMulHigh:
__ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
+ case kMipsMulHighU:
+ __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+ break;
case kMipsDiv:
__ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
=======================================
--- /branches/bleeding_edge/src/compiler/mips/instruction-codes-mips.h Tue
Oct 14 17:26:14 2014 UTC
+++ /branches/bleeding_edge/src/compiler/mips/instruction-codes-mips.h Mon
Nov 3 16:40:54 2014 UTC
@@ -18,6 +18,7 @@
V(MipsSubOvf) \
V(MipsMul) \
V(MipsMulHigh) \
+ V(MipsMulHighU) \
V(MipsDiv) \
V(MipsDivU) \
V(MipsMod) \
=======================================
--- /branches/bleeding_edge/src/compiler/mips/instruction-selector-mips.cc
Thu Oct 30 14:15:20 2014 UTC
+++ /branches/bleeding_edge/src/compiler/mips/instruction-selector-mips.cc
Mon Nov 3 16:40:54 2014 UTC
@@ -305,6 +305,13 @@
Emit(kMipsMulHigh, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
+
+
+void InstructionSelector::VisitUint32MulHigh(Node* node) {
+ MipsOperandGenerator g(this);
+ Emit(kMipsMulHighU, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)),
+ g.UseRegister(node->InputAt(1)));
+}
void InstructionSelector::VisitInt32Div(Node* node) {
=======================================
--- /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Mon Oct 13
14:41:33 2014 UTC
+++ /branches/bleeding_edge/src/mips/macro-assembler-mips.cc Mon Nov 3
16:40:54 2014 UTC
@@ -738,6 +738,28 @@
mult(rs, at);
}
}
+
+
+void MacroAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
+ if (rt.is_reg()) {
+ if (!IsMipsArchVariant(kMips32r6)) {
+ multu(rs, rt.rm());
+ mfhi(rd);
+ } else {
+ muhu(rd, rs, rt.rm());
+ }
+ } else {
+ // li handles the relocation.
+ DCHECK(!rs.is(at));
+ li(at, rt);
+ if (!IsMipsArchVariant(kMips32r6)) {
+ multu(rs, at);
+ mfhi(rd);
+ } else {
+ muhu(rd, rs, at);
+ }
+ }
+}
void MacroAssembler::Multu(Register rs, const Operand& rt) {
=======================================
--- /branches/bleeding_edge/src/mips/macro-assembler-mips.h Mon Oct 13
14:41:33 2014 UTC
+++ /branches/bleeding_edge/src/mips/macro-assembler-mips.h Mon Nov 3
16:40:54 2014 UTC
@@ -593,6 +593,7 @@
DEFINE_INSTRUCTION(Modu);
DEFINE_INSTRUCTION(Mulh);
DEFINE_INSTRUCTION2(Mult);
+ DEFINE_INSTRUCTION(Mulhu);
DEFINE_INSTRUCTION2(Multu);
DEFINE_INSTRUCTION2(Div);
DEFINE_INSTRUCTION2(Divu);
--
--
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