Reviewers: Benedikt Meurer,
Message:
PTAL
Description:
[turbofan] Use load/store indexes as 64-bit registers on arm64.
Since r25024 load/store indexes are 64-bit value but arm64 backend was still
treating them as 32-bit value.
[email protected]
Please review this at https://codereview.chromium.org/698383003/
Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Affected files (+1, -2 lines):
M src/compiler/arm64/code-generator-arm64.cc
Index: src/compiler/arm64/code-generator-arm64.cc
diff --git a/src/compiler/arm64/code-generator-arm64.cc
b/src/compiler/arm64/code-generator-arm64.cc
index
58886ae19ebc06517467cd056c79a35e47a9b356..0c75b7c384327e39fc04d8831e3ea1b46e069231
100644
--- a/src/compiler/arm64/code-generator-arm64.cc
+++ b/src/compiler/arm64/code-generator-arm64.cc
@@ -100,8 +100,7 @@ class Arm64OperandConverter FINAL : public
InstructionOperandConverter {
return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
case kMode_MRR:
*first_index += 2;
- return MemOperand(InputRegister(index + 0), InputRegister(index +
1),
- SXTW);
+ return MemOperand(InputRegister(index + 0), InputRegister(index +
1));
}
UNREACHABLE();
return MemOperand(no_reg);
--
--
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