Reviewers: paul.l..., dusmil.imgtec, gergely.kis.imgtec, akos.palfi,
Message:
PTAL: I am not sure if padding nop should be added to the code
block "saved" by
BlockTrampolinePoolFor() on mip64el in function
CodeGenerator::AssembleArchTableSwitch(). Or if the code block moved then we
need the same padding?
Description:
MIPS: Fix 'MIPS: [turbofan] Optimize certain chains of Branch into a
Switch.'
Space and time constants fixed. Delay slot optimisations added.
BUG=
Please review this at https://codereview.chromium.org/940453003/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+22, -18 lines):
M src/compiler/mips/code-generator-mips.cc
M src/compiler/mips/instruction-selector-mips.cc
M src/compiler/mips64/code-generator-mips64.cc
M src/compiler/mips64/instruction-selector-mips64.cc
Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc
b/src/compiler/mips/code-generator-mips.cc
index
856a69def9c5548015b7f4a24fdc2bcf8175f0b0..58c45816636df1a0f84daf29078317833105cc95
100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -889,9 +889,10 @@ void
CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
MipsOperandConverter i(this, instr);
Register input = i.InputRegister(0);
for (size_t index = 2; index < instr->InputCount(); index += 2) {
- __ Branch(GetLabel(i.InputRpo(index + 1)), eq, input,
- Operand(i.InputInt32(index + 0)));
+ __ li(at, Operand(i.InputInt32(index + 0)));
+ __ beq(input, at, GetLabel(i.InputRpo(index + 1)));
}
+ __ nop(); // Branch delay slot of the last beq.
AssembleArchJump(i.InputRpo(1));
}
@@ -902,12 +903,12 @@ void
CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
size_t const case_count = instr->InputCount() - 2;
Label here;
__ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
+ __ BlockTrampolinePoolFor(case_count + 6);
__ bal(&here);
- __ nop(); // Branch delay slot nop.
+ __ sll(at, input, 2); // Branch delay slot.
__ bind(&here);
- __ sll(at, input, 2);
__ addu(at, at, ra);
- __ lw(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
+ __ lw(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
__ jr(at);
__ nop(); // Branch delay slot nop.
for (size_t index = 0; index < case_count; ++index) {
Index: src/compiler/mips/instruction-selector-mips.cc
diff --git a/src/compiler/mips/instruction-selector-mips.cc
b/src/compiler/mips/instruction-selector-mips.cc
index
30fcb80e6af2df78bbe63650cfe74340335a680e..d723453c017518329fdb440bec63d62e6468a8d2
100644
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -761,9 +761,9 @@ void InstructionSelector::VisitSwitch(Node* node,
BasicBlock* default_branch,
// Determine whether to issue an ArchTableSwitch or an ArchLookupSwitch
// instruction.
- size_t table_space_cost = 4 + value_range;
- size_t table_time_cost = 3;
- size_t lookup_space_cost = 3 + 2 * case_count;
+ size_t table_space_cost = 9 + value_range;
+ size_t table_time_cost = 9;
+ size_t lookup_space_cost = 2 + 2 * case_count;
size_t lookup_time_cost = case_count;
if (case_count > 0 &&
table_space_cost + 3 * table_time_cost <=
Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc
b/src/compiler/mips64/code-generator-mips64.cc
index
7c1288d7549849cae10a892af9862fe0f528747d..14b9eca6adc69d1eb08a0b9ee03123033456eed6
100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -1044,9 +1044,10 @@ void
CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
MipsOperandConverter i(this, instr);
Register input = i.InputRegister(0);
for (size_t index = 2; index < instr->InputCount(); index += 2) {
- __ Branch(GetLabel(i.InputRpo(index + 1)), eq, input,
- Operand(i.InputInt32(index + 0)));
+ __ li(at, Operand(i.InputInt32(index + 0)));
+ __ beq(input, at, GetLabel(i.InputRpo(index + 1)));
}
+ __ nop(); // Branch delay slot of the last beq.
AssembleArchJump(i.InputRpo(1));
}
@@ -1058,16 +1059,18 @@ void
CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
Label here;
__ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
- // Ensure that dd-ed labels goes to 8 byte aligned addresses.
- if ((masm()->pc_offset() & 7) == 0) {
+ // Ensure that dd-ed labels use 8 byte aligned addresses.
+ if ((masm()->pc_offset() & 7) != 0) {
+ __ BlockTrampolinePoolFor(case_count * 2 + 7);
__ nop();
+ } else {
+ __ BlockTrampolinePoolFor(case_count * 2 + 6);
}
__ bal(&here);
- __ nop(); // Branch delay slot nop.
+ __ dsll(at, input, 3); // Branch delay slot.
__ bind(&here);
- __ dsll(at, input, 3);
__ daddu(at, at, ra);
- __ ld(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
+ __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
__ jr(at);
__ nop(); // Branch delay slot nop.
for (size_t index = 0; index < case_count; ++index) {
Index: src/compiler/mips64/instruction-selector-mips64.cc
diff --git a/src/compiler/mips64/instruction-selector-mips64.cc
b/src/compiler/mips64/instruction-selector-mips64.cc
index
713deb6390df7c0f92c22d47cc8bcad0bc162330..779f786468bfa21f46df9e1f36dc60ff6eb60456
100644
--- a/src/compiler/mips64/instruction-selector-mips64.cc
+++ b/src/compiler/mips64/instruction-selector-mips64.cc
@@ -982,9 +982,9 @@ void InstructionSelector::VisitSwitch(Node* node,
BasicBlock* default_branch,
// Determine whether to issue an ArchTableSwitch or an ArchLookupSwitch
// instruction.
- size_t table_space_cost = 4 + value_range;
- size_t table_time_cost = 3;
- size_t lookup_space_cost = 3 + 2 * case_count;
+ size_t table_space_cost = 10 + 2 * value_range;
+ size_t table_time_cost = 10;
+ size_t lookup_space_cost = 2 + 2 * case_count;
size_t lookup_time_cost = case_count;
if (case_count > 0 &&
table_space_cost + 3 * table_time_cost <=
--
--
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