On 2015/02/20 21:52:13, michael_dawson wrote:
At the very least we are going to need changes in the common code to
allow us
to
maintain a dedicated constant pool register and slot in the stack frame.
This
is
because Power architecture does not support pc-relative loads.
We can limit this with a PPC specific guard name but we thought this could
also
be leveraged other platforms like MIPs.
I don't think we need any changes in the common code at all for this:
Somehow
you need to reload the constant pool register at various places (e.g. after
calls etc.), and there is no fundamental reason why this has to be done
from the
stack frame. You can just reload the absolute address again, IIRC this
needs 2
instructions on PPC, so you need some kind of relocation info for this
instruction pair. I don't know if you already have this kind of relocation,
but
ARM (and probably MIPS, too) has it. It's not obvious at all that this is
less
efficient than a memory load from the fram. Let's first get things running
on
PPC with minimal changes to the rest of the system. Tuning can be done later
after extensive benchmarking.
Was your concern with the way we guarded changes in the common code (using
existing
out of line flags) for the base register and slot or that we require
that support at all in the alternate approach.
Regarding the guards: Assume that no OOL-related #defines exist, they will
probably die. Introducing more usages will just make ripping them out later
more
complicated. Regarding register/slot: See above.
https://codereview.chromium.org/882263003/
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