[v8-dev] MIPS: [turbofan] Turn Math.clz32 into an inlinable builtin. (issue 1020223002 by [email protected])

Fri, 20 Mar 2015 06:44:25 -0700

Reviewers: danno, Benedikt Meurer, paul.l..., dusmil.imgtec, akos.palfi.imgtec, gergely.kis.imgtec, 

Description:
MIPS: [turbofan] Turn Math.clz32 into an inlinable builtin.

Port 3aa206b86560da94f895625186295bf07a0301d8

BUG=v8:3952
LOG=n

Please review this at https://codereview.chromium.org/1020223002/

Base URL: https://chromium.googlesource.com/v8/v8.git@master

Affected files (+50, -0 lines):
  M src/compiler/mips/code-generator-mips.cc
  M src/compiler/mips/instruction-codes-mips.h
  M src/compiler/mips/instruction-selector-mips.cc
  M src/compiler/mips64/code-generator-mips64.cc
  M src/compiler/mips64/instruction-codes-mips64.h
  M src/compiler/mips64/instruction-selector-mips64.cc
  M test/unittests/compiler/mips/instruction-selector-mips-unittest.cc
  M test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc


Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc index 12154a9e5a9b40f37726bcb4028b3f785aa7a9c0..7cf7927ab3facc144bf895103fb36b5c908df1ca 100644 
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -496,6 +496,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { 
     case kMipsXor:
       __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
+    case kMipsClz:
+      __ Clz(i.OutputRegister(), i.InputRegister(0));
+      break;
     case kMipsShl:
       if (instr->InputAt(1)->IsRegister()) {
__ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); 
Index: src/compiler/mips/instruction-codes-mips.h
diff --git a/src/compiler/mips/instruction-codes-mips.h b/src/compiler/mips/instruction-codes-mips.h index 3fb48bfbbbc9974b45450b8bb3fcd709e005ab07..82639baab97cb553b59d84eaf4953521056ebf7f 100644 
--- a/src/compiler/mips/instruction-codes-mips.h
+++ b/src/compiler/mips/instruction-codes-mips.h
@@ -26,6 +26,7 @@ namespace compiler {
   V(MipsAnd)                       \
   V(MipsOr)                        \
   V(MipsXor)                       \
+  V(MipsClz)                       \
   V(MipsShl)                       \
   V(MipsShr)                       \
   V(MipsSar)                       \
Index: src/compiler/mips/instruction-selector-mips.cc
diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc index 3c647ed6a1355782238ccbaa612e8c1a09113bc2..1980664701fd498b3be144c891e7414999226a30 100644 
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -265,6 +265,12 @@ void InstructionSelector::VisitWord32Ror(Node* node) {
 }


+void InstructionSelector::VisitWord32Clz(Node* node) {
+  MipsOperandGenerator g(this);
+ Emit(kMipsClz, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); 
+}
+
+
 void InstructionSelector::VisitInt32Add(Node* node) {
   MipsOperandGenerator g(this);

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc index 85b2ffb38f951ed7a1c8fd316b384a14854c5275..6131ec773c2241c3b5c1f9b307eba377cd6baab6 100644 
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -511,6 +511,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { 
     case kMips64Xor:
       __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
+    case kMips64Clz:
+      __ Clz(i.OutputRegister(), i.InputRegister(0));
+      break;
     case kMips64Shl:
       if (instr->InputAt(1)->IsRegister()) {
__ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); 
Index: src/compiler/mips64/instruction-codes-mips64.h
diff --git a/src/compiler/mips64/instruction-codes-mips64.h b/src/compiler/mips64/instruction-codes-mips64.h index 2e578202dc2ba467a919acea6dfae285cabca20f..b184018bd7502080cc5fd15ab612eecd5de03918 100644 
--- a/src/compiler/mips64/instruction-codes-mips64.h
+++ b/src/compiler/mips64/instruction-codes-mips64.h
@@ -31,6 +31,7 @@ namespace compiler {
   V(Mips64And)                      \
   V(Mips64Or)                       \
   V(Mips64Xor)                      \
+  V(Mips64Clz)                      \
   V(Mips64Shl)                      \
   V(Mips64Shr)                      \
   V(Mips64Sar)                      \
Index: src/compiler/mips64/instruction-selector-mips64.cc
diff --git a/src/compiler/mips64/instruction-selector-mips64.cc b/src/compiler/mips64/instruction-selector-mips64.cc index 3eebdb43a59e9d8c5efa1378f18b0d1d1fa596c8..728056f2405a06047235f32b614fbb798b37e262 100644 
--- a/src/compiler/mips64/instruction-selector-mips64.cc
+++ b/src/compiler/mips64/instruction-selector-mips64.cc
@@ -305,6 +305,12 @@ void InstructionSelector::VisitWord32Ror(Node* node) {
 }


+void InstructionSelector::VisitWord32Clz(Node* node) {
+  Mips64OperandGenerator g(this);
+ Emit(kMips64Clz, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); 
+}
+
+
 void InstructionSelector::VisitWord64Ror(Node* node) {
   VisitRRO(this, kMips64Dror, node);
 }
Index: test/unittests/compiler/mips/instruction-selector-mips-unittest.cc
diff --git a/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc b/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc index efe26d22b40b5f68c1b15768aa9ccdab9b1ea96c..bafa89d581d120b7286537f07be2f8271d2fb49f 100644 
--- a/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc
+++ b/test/unittests/compiler/mips/instruction-selector-mips-unittest.cc
@@ -800,6 +800,21 @@ TEST_F(InstructionSelectorTest, Word32EqualWithZero) {
   }
 }

+
+TEST_F(InstructionSelectorTest, Word32Clz) {
+  StreamBuilder m(this, kMachUint32, kMachUint32);
+  Node* const p0 = m.Parameter(0);
+  Node* const n = m.Word32Clz(p0);
+  m.Return(n);
+  Stream s = m.Build();
+  ASSERT_EQ(1U, s.size());
+  EXPECT_EQ(kMipsClz, s[0]->arch_opcode());
+  ASSERT_EQ(1U, s[0]->InputCount());
+  EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+  ASSERT_EQ(1U, s[0]->OutputCount());
+  EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
Index: test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc diff --git a/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc b/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc index ab95023492845522981257098131b2cfbca71b8d..0953de8c40cd8cdad2e23a0dd3b2cce9dfc07d1a 100644 
--- a/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
+++ b/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc
@@ -801,6 +801,21 @@ TEST_F(InstructionSelectorTest, Word64EqualWithZero) {
   }
 }

+
+TEST_F(InstructionSelectorTest, Word32Clz) {
+  StreamBuilder m(this, kMachUint32, kMachUint32);
+  Node* const p0 = m.Parameter(0);
+  Node* const n = m.Word32Clz(p0);
+  m.Return(n);
+  Stream s = m.Build();
+  ASSERT_EQ(1U, s.size());
+  EXPECT_EQ(kMips64Clz, s[0]->arch_opcode());
+  ASSERT_EQ(1U, s[0]->InputCount());
+  EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+  ASSERT_EQ(1U, s[0]->OutputCount());
+  EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8


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