Reviewers: paul.l..., dusmil, akos.palfi.imgtec, gergely.kis.imgtec,
Message:
PTAL,
Is the arch variant checking is OK and should/could we add min/max to
mips32r6
also (in this CL)?
Description:
MIPS64: [turbofan] Support Float64Min and Float64Max.
Port b9ef7d42678d486123445aa17459ff778625bcb0
MIPS64r6 support for Float64Min and Float64Max machine operators using min
and
max.
BUG=
Please review this at https://codereview.chromium.org/1027193002/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+32, -2 lines):
M src/compiler/mips64/code-generator-mips64.cc
M src/compiler/mips64/instruction-codes-mips64.h
M src/compiler/mips64/instruction-selector-mips64.cc
Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc
b/src/compiler/mips64/code-generator-mips64.cc
index
6131ec773c2241c3b5c1f9b307eba377cd6baab6..1a823cd025416b67a20722ad7de855be4832f05e
100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -654,6 +654,14 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ sqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
}
+ case kMips64MaxD:
+ __ max(D, i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
+ case kMips64MinD:
+ __ min(D, i.OutputDoubleRegister(), i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
case kMips64CvtSD: {
__ cvt_s_d(i.OutputSingleRegister(), i.InputDoubleRegister(0));
break;
Index: src/compiler/mips64/instruction-codes-mips64.h
diff --git a/src/compiler/mips64/instruction-codes-mips64.h
b/src/compiler/mips64/instruction-codes-mips64.h
index
b184018bd7502080cc5fd15ab612eecd5de03918..60f696b99a9eececa82d293ba47815136a841113
100644
--- a/src/compiler/mips64/instruction-codes-mips64.h
+++ b/src/compiler/mips64/instruction-codes-mips64.h
@@ -52,6 +52,8 @@ namespace compiler {
V(Mips64DivD) \
V(Mips64ModD) \
V(Mips64SqrtD) \
+ V(Mips64MaxD) \
+ V(Mips64MinD) \
V(Mips64Float64RoundDown) \
V(Mips64Float64RoundTruncate) \
V(Mips64Float64RoundUp) \
Index: src/compiler/mips64/instruction-selector-mips64.cc
diff --git a/src/compiler/mips64/instruction-selector-mips64.cc
b/src/compiler/mips64/instruction-selector-mips64.cc
index
728056f2405a06047235f32b614fbb798b37e262..85f5c60436f2b9681b2229e597c3b35dd011683a
100644
--- a/src/compiler/mips64/instruction-selector-mips64.cc
+++ b/src/compiler/mips64/instruction-selector-mips64.cc
@@ -594,10 +594,30 @@ void InstructionSelector::VisitFloat64Mod(Node* node)
{
}
-void InstructionSelector::VisitFloat64Max(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Max(Node* node) {
+ if (kArchVariant == kMips64r6) {
+ Mips64OperandGenerator g(this);
+ Node* left = node->InputAt(0);
+ Node* right = node->InputAt(1);
+ Emit(kMips64MaxD, g.DefineAsRegister(node), g.UseRegister(left),
+ g.UseRegister(right));
+ } else {
+ UNREACHABLE();
+ }
+}
-void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Min(Node* node) {
+ if (kArchVariant == kMips64r6) {
+ Mips64OperandGenerator g(this);
+ Node* left = node->InputAt(0);
+ Node* right = node->InputAt(1);
+ Emit(kMips64MinD, g.DefineAsRegister(node), g.UseRegister(left),
+ g.UseRegister(right));
+ } else {
+ UNREACHABLE();
+ }
+}
void InstructionSelector::VisitFloat64Sqrt(Node* node) {
--
--
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