Reviewers: ulan, Benedikt Meurer,
Description:
[arm64] Use ubfiz in ARM64 instruction selector
Select ubfiz for (x & mask) << imm where mask is contiguous and imm is
non-zero.
BUG=
Please review this at https://codereview.chromium.org/1161643003/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+71, -0 lines):
M src/compiler/arm64/code-generator-arm64.cc
M src/compiler/arm64/instruction-codes-arm64.h
M src/compiler/arm64/instruction-selector-arm64.cc
M test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
Index: src/compiler/arm64/code-generator-arm64.cc
diff --git a/src/compiler/arm64/code-generator-arm64.cc
b/src/compiler/arm64/code-generator-arm64.cc
index
4c05eb36b1b23066806070fd906c55d1dc4ea48a..91b100b0686e0ed99849f103f22daa0e7676270d
100644
--- a/src/compiler/arm64/code-generator-arm64.cc
+++ b/src/compiler/arm64/code-generator-arm64.cc
@@ -654,6 +654,10 @@ void
CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ Ubfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),
i.InputInt5(2));
break;
+ case kArm64Ubfiz32:
+ __ Ubfiz(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),
+ i.InputInt5(2));
+ break;
case kArm64Bfi:
__ Bfi(i.OutputRegister(), i.InputRegister(1), i.InputInt6(2),
i.InputInt6(3));
Index: src/compiler/arm64/instruction-codes-arm64.h
diff --git a/src/compiler/arm64/instruction-codes-arm64.h
b/src/compiler/arm64/instruction-codes-arm64.h
index
d888c0b1c3d6a9748834de5bbbaecf5422000c16..f76854611ee8b467cab7974ded78d043d2732662
100644
--- a/src/compiler/arm64/instruction-codes-arm64.h
+++ b/src/compiler/arm64/instruction-codes-arm64.h
@@ -72,6 +72,7 @@ namespace compiler {
V(Arm64Sbfx32) \
V(Arm64Ubfx) \
V(Arm64Ubfx32) \
+ V(Arm64Ubfiz32) \
V(Arm64Bfi) \
V(Arm64TestAndBranch32) \
V(Arm64TestAndBranch) \
Index: src/compiler/arm64/instruction-selector-arm64.cc
diff --git a/src/compiler/arm64/instruction-selector-arm64.cc
b/src/compiler/arm64/instruction-selector-arm64.cc
index
3077ade7295e0d2269f639fd914c24dabc046c7a..a739f221085f78034ce713d5464bc5f71a71336c
100644
--- a/src/compiler/arm64/instruction-selector-arm64.cc
+++ b/src/compiler/arm64/instruction-selector-arm64.cc
@@ -641,6 +641,38 @@ void InstructionSelector::VisitWord64Xor(Node* node) {
void InstructionSelector::VisitWord32Shl(Node* node) {
+ Int32BinopMatcher m(node);
+ if (m.left().IsWord32And() && CanCover(node, m.left().node()) &&
+ m.right().IsInRange(1, 31)) {
+ Arm64OperandGenerator g(this);
+ Int32BinopMatcher mleft(m.left().node());
+ if (mleft.right().HasValue()) {
+ uint32_t mask = mleft.right().Value();
+ uint32_t mask_width = base::bits::CountPopulation32(mask);
+ uint32_t mask_msb = base::bits::CountLeadingZeros32(mask);
+ if ((mask_width != 0) && (mask_msb + mask_width == 32)) {
+ uint32_t shift = m.right().Value();
+ DCHECK_EQ(0u, base::bits::CountTrailingZeros32(mask));
+ DCHECK_NE(0u, shift);
+
+ if ((shift + mask_width) >= 32) {
+ // If the mask is contiguous and reaches or extends beyond the
top
+ // bit, only the shift is needed.
+ Emit(kArm64Lsl32, g.DefineAsRegister(node),
+ g.UseRegister(mleft.left().node()),
+ g.UseImmediate(m.right().node()));
+ return;
+ } else {
+ // Select Ubfiz for Shl(And(x, mask), imm) where the mask is
+ // contiguous, and the shift immediate non-zero.
+ Emit(kArm64Ubfiz32, g.DefineAsRegister(node),
+ g.UseRegister(mleft.left().node()),
+ g.UseImmediate(m.right().node()),
g.TempImmediate(mask_width));
+ return;
+ }
+ }
+ }
+ }
VisitRRO(this, kArm64Lsl32, node, kShift32Imm);
}
Index: test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
diff --git
a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
index
3ed52e0ba7f6182351ece11e358badbc06a22b6b..3e36d202e61da628f577b19d09dc019da6c4340f
100644
--- a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
+++ b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
@@ -2429,6 +2429,40 @@ TEST_F(InstructionSelectorTest,
Word32ShrWithWord32Shl) {
}
+TEST_F(InstructionSelectorTest, Word32ShlWithWord32And) {
+ TRACED_FORRANGE(int32_t, shift, 1, 30) {
+ StreamBuilder m(this, kMachInt32, kMachInt32);
+ Node* const p0 = m.Parameter(0);
+ Node* const r =
+ m.Word32Shl(m.Word32And(p0, m.Int32Constant((1 << (31 - shift)) -
1)),
+ m.Int32Constant(shift));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Ubfiz32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+ TRACED_FORRANGE(int32_t, shift, 0, 30) {
+ StreamBuilder m(this, kMachInt32, kMachInt32);
+ Node* const p0 = m.Parameter(0);
+ Node* const r =
+ m.Word32Shl(m.Word32And(p0, m.Int32Constant((1 << (31 - shift)) -
1)),
+ m.Int32Constant(shift + 1));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Lsl32, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+}
+
+
TEST_F(InstructionSelectorTest, Word32Clz) {
StreamBuilder m(this, kMachUint32, kMachUint32);
Node* const p0 = m.Parameter(0);
--
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